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    Subject[PATCH v4 00/12] KVM: x86: Add AMD Guest PerfMonV2 PMU support
    Date
    Starting with Zen4, core PMU on AMD platforms such as Genoa and
    Ryzen-7000 will support PerfMonV2, and it is also compatible with
    legacy PERFCTR_CORE behavior and msr addresses.

    If you don't have access to the hardware specification, the commits
    d6d0c7f681fd..7685665c390d for host perf can also bring a quick
    overview. Its main change is the addition of three msr's equivalent
    to Intel V2, namely global_ctrl, global_status, global_status_clear.

    It is worth noting that this feature is very attractive for reducing the
    overhead of PMU virtualization, since multiple msr accesses to multiple
    counters will be replaced by a single access to the global register,
    plus more accuracy gain when multiple guest counters are used.

    All related testcases are passed on a Genoa box.
    Please feel free to run more tests, add more or share comments.

    Patch 0001-0009 could be applied earlier, which may help reduce
    the burden on industrious reviewers.

    Base: kvm-x86/pmu
    Previous: 20221111102645.82001-1-likexu@tencent.com

    V3 -> V4 Changelog:
    - Compilability of each patch is retained; (Sean)
    - Apply "if (!diff)" style and use the atomic set_bit(); (Sean)
    - First optimize the helper, then expose it in pmu.h; (Sean)
    - Just use scattered X86_FEATURE_PERFMON_V2; (Sean)
    - Drop use of kvm_cpu_cap_has() when refresh; (Sean)
    - Use tweaked kvm_pmu_cap.num_counters_gp; (Sean)
    - Sanity check the number of counters enumerated by perf; (Sean)
    - Apply an if-elif-else sequence for number of counters; (Sean)
    - Refine commits messages to provide hidden information; (Sean)
    - Apply kvm_cpu_cap_check_and_set() when enable_pmu; (Sean)
    - Fix a coner case when user sets GLOBAL_STATUS reserved bits;
    - For AMD GLOBAL_STATUS, writes are ignored as host does;
    - For AMD GLOBAL_CTL, none #GP on writes as host does;
    - For AMD GLOBAL_STATUS_CLR, none #GP on writes as host does;

    Like Xu (11):
    KVM: x86/pmu: Rename pmc_is_enabled() to pmc_is_globally_enabled()
    KVM: x86/pmu: Rewrite reprogram_counters() to improve performance
    KVM: x86/pmu: Expose reprogram_counters() in pmu.h
    KVM: x86/pmu: Error when user sets the GLOBAL_STATUS reserved bits
    KVM: x86/pmu: Make part of the Intel v2 PMU MSRs handling x86 generic
    KVM: x86/cpuid: Use fast return for cpuid "0xa" leaf when !enable_pmu
    KVM: x86/pmu: Disable vPMU if the minimum num of counters isn't met
    KVM: x86/pmu: Forget PERFCTR_CORE if the min num of counters isn't met
    KVM: x86/cpuid: Add X86_FEATURE_PERFMON_V2 as a scattered flag
    KVM: x86/svm/pmu: Add AMD PerfMonV2 support
    KVM: x86/cpuid: Add AMD CPUID ExtPerfMonAndDbg leaf 0x80000022

    Sean Christopherson (1):
    KVM: VMX: Refactor intel_pmu_set_msr() to align with other set_msr()
    helpers

    arch/x86/include/asm/kvm-x86-pmu-ops.h | 1 -
    arch/x86/kvm/cpuid.c | 26 +++++-
    arch/x86/kvm/pmu.c | 69 +++++++++++++--
    arch/x86/kvm/pmu.h | 35 +++++++-
    arch/x86/kvm/reverse_cpuid.h | 7 ++
    arch/x86/kvm/svm/pmu.c | 62 +++++++++-----
    arch/x86/kvm/svm/svm.c | 17 +++-
    arch/x86/kvm/vmx/pmu_intel.c | 114 +++++++------------------
    arch/x86/kvm/x86.c | 10 +++
    9 files changed, 223 insertions(+), 118 deletions(-)

    --
    2.39.1

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