Messages in this thread | | | Date | Fri, 10 Feb 2023 14:28:29 +0200 | Subject | Re: [PATCH v2 4/5] arm64: dst: qcom: sm8450: switch to usb3/dp combo phy | From | Dmitry Baryshkov <> |
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On 10/02/2023 12:34, Neil Armstrong wrote: > The QMP PHY is a USB3/DP combo phy, switch to the newly > documented bindings and register the clocks to the GCC > and DISPCC controllers. > > Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> > --- > arch/arm64/boot/dts/qcom/sm8450.dtsi | 41 ++++++++++++------------------------ > 1 file changed, 14 insertions(+), 27 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi > index d66dcd8fe61f..6248adc546f2 100644 > --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi > @@ -748,7 +748,7 @@ gcc: clock-controller@100000 { > <&ufs_mem_phy_lanes 0>, > <&ufs_mem_phy_lanes 1>, > <&ufs_mem_phy_lanes 2>, > - <0>; > + <&usb_1_qmpphy 0>; > clock-names = "bi_tcxo", > "sleep_clk", > "pcie_0_pipe_clk",
Same comments as for patch 2, please use new defines for the QMP PHY clocks and PHY enumeration
-- With best wishes Dmitry
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