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    Subject[PATCH 10/12] riscv: dts: starfive: jh7100: Add ccache DT node
    Date
    Provide a DT node for the Sifive Composable Cache controller found on
    the StarFive JH7100 SoC.

    Note this is also used to support non-coherent DMA.

    Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
    ---
    arch/riscv/boot/dts/starfive/jh7100.dtsi | 16 ++++++++++++++++
    1 file changed, 16 insertions(+)

    diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi
    index 7109e70fdab8..88f91bc5753b 100644
    --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
    +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
    @@ -32,6 +32,7 @@ U74_0: cpu@0 {
    i-tlb-sets = <1>;
    i-tlb-size = <32>;
    mmu-type = "riscv,sv39";
    + next-level-cache = <&ccache>;
    riscv,isa = "rv64imafdc";
    tlb-split;

    @@ -57,6 +58,7 @@ U74_1: cpu@1 {
    i-tlb-sets = <1>;
    i-tlb-size = <32>;
    mmu-type = "riscv,sv39";
    + next-level-cache = <&ccache>;
    riscv,isa = "rv64imafdc";
    tlb-split;

    @@ -116,6 +118,20 @@ soc {
    ranges;
    dma-noncoherent;

    + ccache: cache-controller@2010000 {
    + compatible = "starfive,jh7100-ccache", "cache";
    + reg = <0x0 0x2010000 0x0 0x1000>,
    + <0x0 0x8000000 0x0 0x2000000>;
    + reg-names = "control", "sideband";
    + interrupts = <128>, <130>, <131>, <129>;
    + cache-block-size = <64>;
    + cache-level = <2>;
    + cache-sets = <2048>;
    + cache-size = <2097152>;
    + cache-unified;
    + uncached-offset = <0xf 0x80000000>;
    + };
    +
    clint: clint@2000000 {
    compatible = "starfive,jh7100-clint", "sifive,clint0";
    reg = <0x0 0x2000000 0x0 0x10000>;
    --
    2.39.1
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