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    SubjectRE: [PATCH 1/2] dt-bindings: phy: realtek: Add Realtek DHC RTD SoC PCIe PHY
    Date
    Hi Krzysztof,

    Thank you for the review.

    >On 01/12/2023 11:52, Tzuyi Chang wrote:
    >> + "#phy-cells":
    >> + const: 0
    >> +
    >> + nvmem-cells:
    >> + maxItems: 1
    >> + description:
    >> + Phandle to nvmem cell that contains 'Tx swing trim'
    >> + tuning parameter value for PCIe phy.
    >> +
    >> + nvmem-cell-names:
    >> + items:
    >> + - const: tx_swing_trim
    >> +
    >> + realtek,pcie-syscon:
    >> + $ref: /schemas/types.yaml#/definitions/phandle
    >> + description: phandle of syscon used to control PCIe MDIO register.
    >
    >Why this does not have reg property but syscon? This looks hacky.
    >

    Our PCIe PHY driver needs to access two registers:
    1. PCIe MDIO register: Utilized for configuring the PCIe PHY.
    2. PCIe MAC Link Control and Link Status Register: Use to get the current
    link speed for calibration purposes.

    Both these registers reside within the PCIe controller registers. The PCIe
    driver has mapped these register address region, so I use regmap to access
    these registers.

    >Where is the DTS of your platform so we can verify the bindings? In the past
    >Realtek bindings and DTS were sent without testing.

    The bindings and DTS for our platform are continuously being adjusted for the upstream.

    Therefore, I only modified and tested the DTS node of the binding documentations I submitted.
    The DTS node is the same as the examples in the binding documentation. I tested it using the
    command "make dtbs_check DT_SCHEMA_FILES=..." without encountering any errors.

    >> +
    >> +required:
    >> + - compatible
    >> + - realtek,pcie-syscon
    >> + - "#phy-cells"
    >> +
    >> +additionalProperties: false
    >> +
    >> +examples:
    >> + - |
    >> + pcie1_phy {
    >
    >phy {
    >

    I will fix it in the next version.

    Thanks,
    Tzuyi Chang
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