Messages in this thread | | | From | JeeHeng Sia <> | Subject | RE: [PATCH v1 06/16] clk: starfive: Add JH8100 System clock generator driver | Date | Thu, 21 Dec 2023 00:45:40 +0000 |
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> -----Original Message----- > From: Emil Renner Berthing <emil.renner.berthing@canonical.com> > Sent: Wednesday, December 20, 2023 9:08 PM > To: JeeHeng Sia <jeeheng.sia@starfivetech.com>; Emil Renner Berthing <emil.renner.berthing@canonical.com>; kernel@esmil.dk; > conor@kernel.org; robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org; paul.walmsley@sifive.com; palmer@dabbelt.com; > aou@eecs.berkeley.edu; mturquette@baylibre.com; sboyd@kernel.org; p.zabel@pengutronix.de; Hal Feng > <hal.feng@starfivetech.com>; Xingyu Wu <xingyu.wu@starfivetech.com> > Cc: linux-riscv@lists.infradead.org; devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; linux-clk@vger.kernel.org; Leyfoon Tan > <leyfoon.tan@starfivetech.com> > Subject: RE: [PATCH v1 06/16] clk: starfive: Add JH8100 System clock generator driver > > JeeHeng Sia wrote: [...] > > > > > > If you're just using this for testing on FPGAs you can create dummy fixed > > > clocks in the device tree for the PLLs that this driver can consume. Then > > > later when you have a PLL driver you can replace those fixed clocks with the > > > output of that driver. > > The PLL fixed clocks were created in the C code. I interpret this message > > as a suggestion to create a PLL fixed clock in the DT? > > Yes, then you don't need to change the clock driver and its bindings but just > need to update the clock references to the PLL driver once you have that. Ok. > > /Emil
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