Messages in this thread | ![/](/images/icornerl.gif) | | From | "Tian, Kevin" <> | Subject | RE: [RFC PATCH 6/6] iommu/amd: Introduce nested translation support | Date | Fri, 15 Dec 2023 07:45:55 +0000 |
| |
> From: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> > Sent: Wednesday, December 13, 2023 12:02 AM > > To support nested translation on AMD IOMMU, the driver needs to > program DTE[GCR3 Table Root Pointer] with the address provided by > the guest via struct iommu_hwpt_amd_v2, which is passed as a parameter > of the struct iommu_ops.domain_alloc_user() with the flag > IOMMU_HWPT_ALLOC_NEST_PARENT. > > Note that current implementation only support GCR3TRPMode for > nested translation, which uses GPA to program GCR3 Table Root Pointer. >
means there is a plan to support another mode in the future or actually the nested translation requires GCR3TRPMode as a functional requirement? imho the point of GPA is assumed in the nested configuration in concept...
| ![\](/images/icornerr.gif) |