Messages in this thread | | | Date | Thu, 9 Nov 2023 16:32:36 +0800 | Subject | Re: [PATCH v2 1/3] net: phy: at803x: add QCA8084 ethernet phy support | From | Jie Luo <> |
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On 11/8/2023 8:12 PM, Maxime Chevallier wrote: > Hello, > > On Wed, 8 Nov 2023 19:34:43 +0800 > Luo Jie <quic_luoj@quicinc.com> wrote: > >> Add qca8084 PHY support, which is four-port PHY with maximum >> link capability 2.5G, the features of each port is almost same >> as QCA8081 and slave seed config is not needed. >> >> Three kind of interface modes supported by qca8084. >> PHY_INTERFACE_MODE_QUSGMII, PHY_INTERFACE_MODE_2500BASEX and >> PHY_INTERFACE_MODE_SGMII. >> >> The PCS(serdes) and clock are also needed to be configured to >> bringup qca8084 PHY, which will be added in the pcs driver. >> >> The additional CDT configurations used for qca8084. >> >> Signed-off-by: Luo Jie <quic_luoj@quicinc.com> >> --- >> drivers/net/phy/at803x.c | 48 ++++++++++++++++++++++++++++++++++++++++ >> 1 file changed, 48 insertions(+) > > [...] > >> @@ -1824,6 +1828,21 @@ static int qca808x_read_status(struct phy_device *phydev) >> return ret; >> >> if (phydev->link) { >> + /* There are two PCSs available for QCA8084, which support the following >> + * interface modes. >> + * >> + * 1. PHY_INTERFACE_MODE_QUSGMII utilizes PCS1 for all available 4 ports, >> + * which is for all link speeds. >> + * >> + * 2. PHY_INTERFACE_MODE_2500BASEX utilizes PCS0 for the fourth port, >> + * which is only for the link speed 2500M same as QCA8081. >> + * >> + * 3. PHY_INTERFACE_MODE_SGMII utilizes PCS0 for the fourth port, >> + * which is for the link speed 10M, 100M and 1000M same as QCA8081. >> + */ >> + if (phydev->interface == PHY_INTERFACE_MODE_QUSGMII) >> + return 0; >> + > > What I understand from this is that this PHY can be used either as a > switch, in which case port 4 would be connected to the host interface > at up to 2.5G, or as a quad-phy, but since it uses QUSGMII the link > speed would be limited to 1G per-port, is that correct ?
When the PHY works on the interface mode QUSGMII for quad-phy, all 4 PHYs can support to the max link speed 2.5G, actually the PHY can support to max link speed 2.5G for all supported interface modes including qusgmii and sgmii.
> > However the get_features function seems to build the supported modes > set by reading some capabilities registers : > > static int qca808x_get_features(struct phy_device *phydev) > { > [...] > ret = phy_read_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_CHIP_TYPE); > if (ret < 0) > return ret; > > if (QCA808X_PHY_CHIP_TYPE_1G & ret) > linkmode_clear_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported); > [...] > } > > Wouldn't port 4 report 2.5G capabilities then ? Maybe you need to > mask-out the 2.5G bit if the interface is qusgmii. > > Best regards, > > Maxime
All ports including port4 support 2.5G capability for the supported interface mode.
Thanks Maxime for the review.
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