Messages in this thread | | | From | Namhyung Kim <> | Date | Thu, 9 Nov 2023 13:53:22 -0800 | Subject | Re: [PATCH 1/2] perf tool AMD: Use non-precise cycles as default event on certain Zen2 processors |
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Hi Ravi,
On Tue, Nov 7, 2023 at 12:34 AM Ravi Bangoria <ravi.bangoria@amd.com> wrote: > > By default, Perf uses precise cycles event when no explicit event is > specified by user. Precise cycles event is forwarded to ibs_op// pmu > on AMD. However, IBS has hw issue on certain Zen2 processors where > it might raise NMI without sample_valid bit set, which causes Unknown > NMI warnings. (Erratum #1215: IBS (Instruction Based Sampling) Counter > Valid Value May be Incorrect After Exit From Core C6 (CC6) State.) So, > use non-precise cycles as default event on affected processors.
It seems like a kernel issue, do we have a kernel patch not to forward precise cycles or instructions events to IBS on the affected CPUs?
Thanks, Namhyung
> > This does not prevent user to use explicit precise cycles event or > ibs_op// pmu directly. > > Suggested-by: Arnaldo Carvalho de Melo <acme@kernel.org> > Signed-off-by: Ravi Bangoria <ravi.bangoria@amd.com> > ---
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