Messages in this thread | | | From | Ji Sheng Teoh <> | Subject | Re: [PATCH] perf vendor events riscv: add StarFive Dubhe-80 JSON file | Date | Fri, 3 Nov 2023 13:15:30 +0800 |
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>> >> StarFive's Dubhe-80 supports raw event id 0x00 - 0x22. >> The raw events are enabled through PMU node of DT binding. >> >> Example of PMU DT node: >> pmu { >> compatible = "riscv,pmu"; >> riscv,raw-event-to-mhpmcounters = >> /* Event ID 1-31 */ >> <0x00 0x00 0xFFFFFFFF 0xFFFFFFE0 0x00007FF8>, >> /* Event ID 32-33 */ >> <0x00 0x20 0xFFFFFFFF 0xFFFFFFFE 0x00007FF8>, >> /* Event ID 34 */ >> <0x00 0x22 0xFFFFFFFF 0xFFFFFF22 0x00007FF8>; >> }; >> >> Example of Perf stat output: >> [root@user]# perf stat -a \ >> -e access_mmu_stlb \ >> -e miss_mmu_stlb \ >> -e access_mmu_pte_c \ >> -e rob_flush \ >> -e btb_prediction_miss \ >> -e itlb_miss \ >> -e sync_del_fetch_g \ >> -e icache_miss \ >> -e bpu_br_retire \ >> -e bpu_br_miss \ >> -e ret_ins_retire \ >> -e ret_ins_miss \ >> -- openssl speed rsa2048 >> >> Doing 2048 bits private rsa's for 10s: 39 2048 bits private RSA's in >> 10.14s >> Doing 2048 bits public rsa's for 10s: 1563 2048 bits public RSA's in >> 10.00s >> version: 3.0.11 >> built on: Tue Sep 19 13:02:31 2023 UTC >> options: bn(64,64) >> CPUINFO: N/A >> sign verify sign/s verify/s >> rsa 2048 bits 0.260000s 0.006398s 3.8 156.3 >> >> Performance counter stats for 'system wide': >> >> 1338350 access_mmu_stlb >> 1154025 miss_mmu_stlb >> 1162691 access_mmu_pte_c >> 34067 rob_flush >> 11212384 btb_prediction_miss >> 1256242 itlb_miss >> 652523491 sync_del_fetch_g >> 384465 icache_miss >> 64635789 bpu_br_retire >> 323440 bpu_br_miss >> 8785143 ret_ins_retire >> 31236 ret_ins_miss >> >> 20.760822480 seconds time elapsed >> >> Signed-off-by: Ji Sheng Teoh <jisheng.teoh@xxxxxxxxxxxxxxxx> > > Thanks Ji Sheng, > > in adding these events for this new architecture is there a reason not > to add the architecture standard events in > tools/perf/pmu-events/arch/riscv/riscv-sbi-firmware.json ? > https://git.kernel.org/pub/scm/linux/kernel/git/perf/perf-tools-next.git/tree/tools/perf/pmu-events/arch/riscv/riscv-sbi-firmware.json?h=perf-tools-next > > Perhaps it is worth commenting in the commit message whether or not > these events are supported. > > Thanks, > Ian
Thanks Ian for the comment,
The architecture standard events are supported as well. I will include them in v2.
Thanks, Ji Sheng
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