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    Subject[PATCH v2 08/15] clk: qcom: gcc-sm6115: Unregister critical clocks
    Some clocks need to be always-on, but we don't really do anything
    with them, other than calling enable() once and telling Linux they're
    enabled.

    Unregister them to save a couple of bytes and, perhaps more
    importantly, allow for runtime suspend of the clock controller device,
    as CLK_IS_CRITICAL prevents the latter.

    Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
    ---
    drivers/clk/qcom/gcc-sm6115.c | 123 +++---------------------------------------
    1 file changed, 8 insertions(+), 115 deletions(-)

    diff --git a/drivers/clk/qcom/gcc-sm6115.c b/drivers/clk/qcom/gcc-sm6115.c
    index 13e521cd4259..87a2bfe222a3 100644
    --- a/drivers/clk/qcom/gcc-sm6115.c
    +++ b/drivers/clk/qcom/gcc-sm6115.c
    @@ -1586,36 +1586,6 @@ static struct clk_branch gcc_cam_throttle_rt_clk = {
    },
    };

    -static struct clk_branch gcc_camera_ahb_clk = {
    - .halt_reg = 0x17008,
    - .halt_check = BRANCH_HALT_DELAY,
    - .hwcg_reg = 0x17008,
    - .hwcg_bit = 1,
    - .clkr = {
    - .enable_reg = 0x17008,
    - .enable_mask = BIT(0),
    - .hw.init = &(struct clk_init_data){
    - .name = "gcc_camera_ahb_clk",
    - .flags = CLK_IS_CRITICAL,
    - .ops = &clk_branch2_ops,
    - },
    - },
    -};
    -
    -static struct clk_branch gcc_camera_xo_clk = {
    - .halt_reg = 0x17028,
    - .halt_check = BRANCH_HALT,
    - .clkr = {
    - .enable_reg = 0x17028,
    - .enable_mask = BIT(0),
    - .hw.init = &(struct clk_init_data){
    - .name = "gcc_camera_xo_clk",
    - .flags = CLK_IS_CRITICAL,
    - .ops = &clk_branch2_ops,
    - },
    - },
    -};
    -
    static struct clk_branch gcc_camss_axi_clk = {
    .halt_reg = 0x58044,
    .halt_check = BRANCH_HALT,
    @@ -2124,38 +2094,6 @@ static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
    },
    };

    -static struct clk_branch gcc_cpuss_gnoc_clk = {
    - .halt_reg = 0x2b004,
    - .halt_check = BRANCH_HALT_VOTED,
    - .hwcg_reg = 0x2b004,
    - .hwcg_bit = 1,
    - .clkr = {
    - .enable_reg = 0x79004,
    - .enable_mask = BIT(22),
    - .hw.init = &(struct clk_init_data){
    - .name = "gcc_cpuss_gnoc_clk",
    - .flags = CLK_IS_CRITICAL,
    - .ops = &clk_branch2_ops,
    - },
    - },
    -};
    -
    -static struct clk_branch gcc_disp_ahb_clk = {
    - .halt_reg = 0x1700c,
    - .halt_check = BRANCH_HALT,
    - .hwcg_reg = 0x1700c,
    - .hwcg_bit = 1,
    - .clkr = {
    - .enable_reg = 0x1700c,
    - .enable_mask = BIT(0),
    - .hw.init = &(struct clk_init_data){
    - .name = "gcc_disp_ahb_clk",
    - .flags = CLK_IS_CRITICAL,
    - .ops = &clk_branch2_ops,
    - },
    - },
    -};
    -
    static struct clk_regmap_div gcc_disp_gpll0_clk_src = {
    .reg = 0x17058,
    .shift = 0,
    @@ -2215,20 +2153,6 @@ static struct clk_branch gcc_disp_throttle_core_clk = {
    },
    };

    -static struct clk_branch gcc_disp_xo_clk = {
    - .halt_reg = 0x1702c,
    - .halt_check = BRANCH_HALT,
    - .clkr = {
    - .enable_reg = 0x1702c,
    - .enable_mask = BIT(0),
    - .hw.init = &(struct clk_init_data){
    - .name = "gcc_disp_xo_clk",
    - .flags = CLK_IS_CRITICAL,
    - .ops = &clk_branch2_ops,
    - },
    - },
    -};
    -
    static struct clk_branch gcc_gp1_clk = {
    .halt_reg = 0x4d000,
    .halt_check = BRANCH_HALT,
    @@ -2283,22 +2207,6 @@ static struct clk_branch gcc_gp3_clk = {
    },
    };

    -static struct clk_branch gcc_gpu_cfg_ahb_clk = {
    - .halt_reg = 0x36004,
    - .halt_check = BRANCH_HALT,
    - .hwcg_reg = 0x36004,
    - .hwcg_bit = 1,
    - .clkr = {
    - .enable_reg = 0x36004,
    - .enable_mask = BIT(0),
    - .hw.init = &(struct clk_init_data){
    - .name = "gcc_gpu_cfg_ahb_clk",
    - .flags = CLK_IS_CRITICAL,
    - .ops = &clk_branch2_ops,
    - },
    - },
    -};
    -
    static struct clk_branch gcc_gpu_gpll0_clk_src = {
    .halt_check = BRANCH_HALT_DELAY,
    .clkr = {
    @@ -2771,22 +2679,6 @@ static struct clk_branch gcc_sdcc2_apps_clk = {
    },
    };

    -static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = {
    - .halt_reg = 0x2b06c,
    - .halt_check = BRANCH_HALT_VOTED,
    - .hwcg_reg = 0x2b06c,
    - .hwcg_bit = 1,
    - .clkr = {
    - .enable_reg = 0x79004,
    - .enable_mask = BIT(0),
    - .hw.init = &(struct clk_init_data){
    - .name = "gcc_sys_noc_cpuss_ahb_clk",
    - .flags = CLK_IS_CRITICAL,
    - .ops = &clk_branch2_ops,
    - },
    - },
    -};
    -
    static struct clk_branch gcc_sys_noc_ufs_phy_axi_clk = {
    .halt_reg = 0x45098,
    .halt_check = BRANCH_HALT,
    @@ -3272,8 +3164,6 @@ static struct clk_regmap *gcc_sm6115_clocks[] = {
    [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
    [GCC_CAM_THROTTLE_NRT_CLK] = &gcc_cam_throttle_nrt_clk.clkr,
    [GCC_CAM_THROTTLE_RT_CLK] = &gcc_cam_throttle_rt_clk.clkr,
    - [GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr,
    - [GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr,
    [GCC_CAMSS_AXI_CLK] = &gcc_camss_axi_clk.clkr,
    [GCC_CAMSS_AXI_CLK_SRC] = &gcc_camss_axi_clk_src.clkr,
    [GCC_CAMSS_CAMNOC_ATB_CLK] = &gcc_camss_camnoc_atb_clk.clkr,
    @@ -3322,20 +3212,16 @@ static struct clk_regmap *gcc_sm6115_clocks[] = {
    [GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr,
    [GCC_CAMSS_TOP_AHB_CLK_SRC] = &gcc_camss_top_ahb_clk_src.clkr,
    [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
    - [GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr,
    - [GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr,
    [GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr,
    [GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr,
    [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
    [GCC_DISP_THROTTLE_CORE_CLK] = &gcc_disp_throttle_core_clk.clkr,
    - [GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr,
    [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
    [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
    [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
    [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
    [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
    [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
    - [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,
    [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
    [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
    [GCC_GPU_IREF_CLK] = &gcc_gpu_iref_clk.clkr,
    @@ -3376,7 +3262,6 @@ static struct clk_regmap *gcc_sm6115_clocks[] = {
    [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
    [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
    [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
    - [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr,
    [GCC_SYS_NOC_UFS_PHY_AXI_CLK] = &gcc_sys_noc_ufs_phy_axi_clk.clkr,
    [GCC_SYS_NOC_USB3_PRIM_AXI_CLK] = &gcc_sys_noc_usb3_prim_axi_clk.clkr,
    [GCC_UFS_CLKREF_CLK] = &gcc_ufs_clkref_clk.clkr,
    @@ -3513,6 +3398,14 @@ static int gcc_sm6115_probe(struct platform_device *pdev)
    clk_alpha_pll_configure(&gpll10, regmap, &gpll10_config);
    clk_alpha_pll_configure(&gpll11, regmap, &gpll11_config);

    + qcom_branch_set_clk_en(regmap, 0x17008); /* GCC_CAMERA_AHB_CLK */
    + qcom_branch_set_clk_en(regmap, 0x17028); /* GCC_CAMERA_XO_CLK */
    + qcom_branch_set_clk_en(regmap, 0x2b004); /* GCC_CPUSS_GNOC_CLK */
    + qcom_branch_set_clk_en(regmap, 0x1700c); /* GCC_DISP_AHB_CLK */
    + qcom_branch_set_clk_en(regmap, 0x1702c); /* GCC_DISP_XO_CLK */
    + qcom_branch_set_clk_en(regmap, 0x36004); /* GCC_GPU_CFG_AHB_CLK */
    + qcom_branch_set_clk_en(regmap, 0x2b06c); /* GCC_SYS_NOC_CPUSS_AHB_CLK */
    +
    return qcom_cc_really_probe(pdev, &gcc_sm6115_desc, regmap);
    }

    --
    2.43.0

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