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    Subject[PATCH 3/6] net: ravb: Make write access to CXR35 first before accessing other EMAC registers
    Date
    From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

    Hardware manual of RZ/G3S (and RZ/G2L) specifies the following on the
    description of CXR35 register (chapter "PHY interface select register
    (CXR35)"): "After release reset, make write-access to this register before
    making write-access to other registers (except MDIOMOD). Even if not need
    to change the value of this register, make write-access to this register
    at least one time. Because RGMII/MII MODE is recognized by accessing this
    register".

    The setup procedure for EMAC module (chapter "Setup procedure" of RZ/G3S,
    RZ/G2L manuals) specifies the E-MAC.CXR35 register is the first EMAC
    register that is to be configured.

    Note [A] from chapter "PHY interface select register (CXR35)" specifies
    the following:
    [A] The case which CXR35 SEL_XMII is used for the selection of RGMII/MII
    in APB Clock 100 MHz.
    (1) To use RGMII interface, Set ‘H’03E8_0000’ to this register.
    (2) To use MII interface, Set ‘H’03E8_0002’ to this register.

    Take into account these indication.

    Fixes: 1089877ada8d ("ravb: Add RZ/G2L MII interface support")
    Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
    Reviewed-by: Sergey Shtylyov <s.shtylyov@omp.ru>
    ---

    Changes since [1]:
    - collected Rb tag

    [1] https://lore.kernel.org/all/20231120084606.4083194-1-claudiu.beznea.uj@bp.renesas.com/

    drivers/net/ethernet/renesas/ravb_main.c | 17 +++++++++--------
    1 file changed, 9 insertions(+), 8 deletions(-)

    diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c
    index cd3474168452..2d4f4fb3d16e 100644
    --- a/drivers/net/ethernet/renesas/ravb_main.c
    +++ b/drivers/net/ethernet/renesas/ravb_main.c
    @@ -515,6 +515,15 @@ static void ravb_emac_init_gbeth(struct net_device *ndev)
    {
    struct ravb_private *priv = netdev_priv(ndev);

    + if (priv->phy_interface == PHY_INTERFACE_MODE_MII) {
    + ravb_write(ndev, (1000 << 16) | CXR35_SEL_XMII_MII, CXR35);
    + ravb_modify(ndev, CXR31, CXR31_SEL_LINK0 | CXR31_SEL_LINK1, 0);
    + } else {
    + ravb_write(ndev, (1000 << 16) | CXR35_SEL_XMII_RGMII, CXR35);
    + ravb_modify(ndev, CXR31, CXR31_SEL_LINK0 | CXR31_SEL_LINK1,
    + CXR31_SEL_LINK0);
    + }
    +
    /* Receive frame limit set register */
    ravb_write(ndev, GBETH_RX_BUFF_MAX + ETH_FCS_LEN, RFLR);

    @@ -537,14 +546,6 @@ static void ravb_emac_init_gbeth(struct net_device *ndev)

    /* E-MAC interrupt enable register */
    ravb_write(ndev, ECSIPR_ICDIP, ECSIPR);
    -
    - if (priv->phy_interface == PHY_INTERFACE_MODE_MII) {
    - ravb_modify(ndev, CXR31, CXR31_SEL_LINK0 | CXR31_SEL_LINK1, 0);
    - ravb_write(ndev, (1000 << 16) | CXR35_SEL_XMII_MII, CXR35);
    - } else {
    - ravb_modify(ndev, CXR31, CXR31_SEL_LINK0 | CXR31_SEL_LINK1,
    - CXR31_SEL_LINK0);
    - }
    }

    static void ravb_emac_init_rcar(struct net_device *ndev)
    --
    2.39.2
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