Messages in this thread | | | Date | Thu, 23 Nov 2023 11:57:56 +0100 | Subject | Re: [net PATCH 5/5] octeontx2-af: Update Tx link register range | From | Wojciech Drewek <> |
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On 23.11.2023 06:59, Geetha sowjanya wrote: > On new silicons the TX channels for transmit level has increased.
Will it still work with older silicon?
> This patch fixes the respective register offset range to > configure the newly added channels. > > Fixes: b279bbb3314e ("octeontx2-af: NIX Tx scheduler queue config support") > Signed-off-by: Rahul Bhansali <rbhansali@marvell.com>
What Rahul's signed-off stands for?
> Signed-off-by: Geetha sowjanya <gakula@marvell.com> > --- > drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.c > index b3150f053291..d46ac29adb96 100644 > --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.c > +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.c > @@ -31,8 +31,8 @@ static struct hw_reg_map txsch_reg_map[NIX_TXSCH_LVL_CNT] = { > {NIX_TXSCH_LVL_TL4, 3, 0xFFFF, {{0x0B00, 0x0B08}, {0x0B10, 0x0B18}, > {0x1200, 0x12E0} } }, > {NIX_TXSCH_LVL_TL3, 4, 0xFFFF, {{0x1000, 0x10E0}, {0x1600, 0x1608}, > - {0x1610, 0x1618}, {0x1700, 0x17B0} } }, > - {NIX_TXSCH_LVL_TL2, 2, 0xFFFF, {{0x0E00, 0x0EE0}, {0x1700, 0x17B0} } }, > + {0x1610, 0x1618}, {0x1700, 0x17C8} } }, > + {NIX_TXSCH_LVL_TL2, 2, 0xFFFF, {{0x0E00, 0x0EE0}, {0x1700, 0x17C8} } }, > {NIX_TXSCH_LVL_TL1, 1, 0xFFFF, {{0x0C00, 0x0D98} } }, > }; >
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