Messages in this thread | | | From | Linus Walleij <> | Date | Thu, 23 Nov 2023 08:59:48 +0100 | Subject | Re: [PATCH 0/4] arm64: an optimization for AmpereOne |
| |
On Wed, Nov 22, 2023 at 10:29 AM Huang Shijie <shijie@os.amperecomputing.com> wrote:
> 0) Background: > We found that AmpereOne benefits from aggressive prefetches when > using 4K page size. > > 1) This patch: > 1.1) adds new WORKAROUND_AMPERE_AC03_PREFETCH capability. > 1.2) uses MIDR_AMPERE1 to filter the processor. > 1.3) uses alternative_if to alternative the code > for AmpereOne. > 1.4) adds software prefetches for the specific loop. > Also add a macro add_prefetch. > > 2) Test result: > In hugetlb or tmpfs, We can get big seqential read performance improvement > up to 1.3x ~ 1.4x.
In June 2022 Fujitsu tried to add a similar feature for A64FX, here is the essence of my feedback from back then, it applies here as well: https://lore.kernel.org/linux-arm-kernel/CACRpkdbPLFOoPdX4L6ABV8GKpC8cQGP3s2aN2AvRHEK49U9VMg@mail.gmail.com/#t
TL;DR: this is a hack, if you want to accelerate the memory hierarchy, then work with the MM developers to figure out how to do that in a structured and scientific way that will work with any prefetching hardware on any CPU.
Yours, Linus Walleij
| |