Messages in this thread | | | Date | Thu, 23 Nov 2023 13:14:11 +0530 | Subject | Re: [PATCH 1/6] dt-bindings: usb: dwc3: Clean up hs_phy_irq in bindings | From | Krishna Kurapati PSSNV <> |
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On 11/23/2023 1:11 PM, Krzysztof Kozlowski wrote: > On 22/11/2023 20:13, Krishna Kurapati wrote: >> The high speed related interrupts present on QC targets are as follows: >> >> dp/dm Irq's >> These IRQ's directly reflect changes on the DP/DM pads of the SoC. These >> are used as wakeup interrupts only on SoCs with non-QUSBb2 targets with >> exception of SDM670/SDM845/SM6350. >> >> qusb2_phy irq >> SoCs with QUSB2 PHY do not have separate DP/DM IRQs and expose only a >> single IRQ whose behavior can be modified by the QUSB2PHY_INTR_CTRL >> register. The required DPSE/DMSE configuration is done in >> QUSB2PHY_INTR_CTRL register of phy address space. >> >> hs_phy_irq >> This is completely different from the above two and is present on all >> targets with exception of a few IPQ ones. The interrupt is not enabled by >> default and its functionality is mutually exclusive of qusb2_phy on QUSB >> targets and DP/DM on femto phy targets. >> >> The DTs of several QUSB2 PHY based SoCs incorrectly define "hs_phy_irq" >> when they should have been "qusb2_phy_irq". On Femto phy targets, the >> "hs_phy_irq" mentioned is either the actual "hs_phy_irq" or "pwr_event", >> neither of which would never be triggered directly are non-functional >> currently. The implementation tries to clean up this issue by addressing >> the discrepencies involved and fixing the hs_phy_irq's in respective DT's. >> >> Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com> >> --- >> .../devicetree/bindings/usb/qcom,dwc3.yaml | 125 ++++++++++-------- >> 1 file changed, 69 insertions(+), 56 deletions(-) >> >> diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml >> index e889158ca205..4a46346e2ead 100644 >> --- a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml >> +++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml >> @@ -17,20 +17,25 @@ properties: >> - qcom,ipq5018-dwc3 >> - qcom,ipq5332-dwc3 >> - qcom,ipq6018-dwc3 >> + - qcom,ipq6018-dwc3-sec > > I could not understand from commit msg why you are adding new compatible > and what it is supposed to fix. > > The entire diff is huge thus difficult to review. Why fixing hs_phy_irq > causes three new interrupts being added?
Some targets have two controllers where the second one is only HS capable and doesn't have ss_phy_irq. In such cases to make it clear in bindings, I added a suffix "-sec" and accordingly changed in DT as well. Should've put this in commit text.
>> - qcom,ipq8064-dwc3 >> - qcom,ipq8074-dwc3 >> - qcom,ipq9574-dwc3 >> - qcom,msm8953-dwc3 >> - qcom,msm8994-dwc3 >> - qcom,msm8996-dwc3 >> + - qcom,msm8996-dwc3-sec >> - qcom,msm8998-dwc3 >> - qcom,qcm2290-dwc3 >> - qcom,qcs404-dwc3 >> - qcom,sa8775p-dwc3 >> + - qcom,sa8775p-dwc3-ter > > Ter? > Tertiary controller.
Regards, Krishna,
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