lkml.org 
[lkml]   [2023]   [Nov]   [22]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
    /
    From
    Date
    SubjectRe: [PATCH 3/7] phy: qcom-qmp: pcs: Add v7 register offsets
    On Wed, 22 Nov 2023 at 12:04, Abel Vesa <abel.vesa@linaro.org> wrote:
    >
    > The X1E80100 platform bumps the HW version of QMP phy to v7 for USB,
    > and PCIe. Add the new PCS offsets in a dedicated header file.
    >
    > Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
    > ---
    > drivers/phy/qualcomm/phy-qcom-qmp-pcs-v7.h | 28 ++++++++++++++++++++++++++++
    > drivers/phy/qualcomm/phy-qcom-qmp.h | 2 ++
    > 2 files changed, 30 insertions(+)
    >
    > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v7.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v7.h
    > new file mode 100644
    > index 000000000000..520f28d802f6
    > --- /dev/null
    > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v7.h
    > @@ -0,0 +1,28 @@
    > +/* SPDX-License-Identifier: GPL-2.0 */
    > +/*
    > + * Copyright (c) 2023, Linaro Limited
    > + */
    > +
    > +#ifndef QCOM_PHY_QMP_PCS_V7_H_
    > +#define QCOM_PHY_QMP_PCS_V7_H_
    > +
    > +/* Only for QMP V6 PHY - USB/PCIe PCS registers */

    V7

    > +
    > +#define QPHY_V7_PCS_LOCK_DETECT_CONFIG1 0xc4
    > +#define QPHY_V7_PCS_LOCK_DETECT_CONFIG2 0xc8
    > +#define QPHY_V7_PCS_LOCK_DETECT_CONFIG3 0xcc
    > +#define QPHY_V7_PCS_LOCK_DETECT_CONFIG6 0xd8
    > +#define QPHY_V7_PCS_REFGEN_REQ_CONFIG1 0xdc
    > +#define QPHY_V7_PCS_RX_SIGDET_LVL 0x188
    > +#define QPHY_V7_PCS_RCVR_DTCT_DLY_P1U2_L 0x190
    > +#define QPHY_V7_PCS_RCVR_DTCT_DLY_P1U2_H 0x194
    > +#define QPHY_V7_PCS_RATE_SLEW_CNTRL1 0x198
    > +#define QPHY_V7_PCS_RX_CONFIG 0x1b0
    > +#define QPHY_V7_PCS_ALIGN_DETECT_CONFIG1 0x1c0
    > +#define QPHY_V7_PCS_ALIGN_DETECT_CONFIG2 0x1c4
    > +#define QPHY_V7_PCS_PCS_TX_RX_CONFIG 0x1d0
    > +#define QPHY_V7_PCS_EQ_CONFIG1 0x1dc
    > +#define QPHY_V7_PCS_EQ_CONFIG2 0x1e0
    > +#define QPHY_V7_PCS_EQ_CONFIG5 0x1ec
    > +
    > +#endif
    > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
    > index 71f063f4a56e..21f6a56e7ae3 100644
    > --- a/drivers/phy/qualcomm/phy-qcom-qmp.h
    > +++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
    > @@ -44,6 +44,8 @@
    >
    > #include "phy-qcom-qmp-pcs-v6_20.h"
    >
    > +#include "phy-qcom-qmp-pcs-v7.h"
    > +
    > /* Only for QMP V3 & V4 PHY - DP COM registers */
    > #define QPHY_V3_DP_COM_PHY_MODE_CTRL 0x00
    > #define QPHY_V3_DP_COM_SW_RESET 0x04
    >
    > --
    > 2.34.1
    >
    >


    --
    With best wishes
    Dmitry

    \
     
     \ /
      Last update: 2023-11-22 11:16    [W:4.602 / U:0.012 seconds]
    ©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site