Messages in this thread | | | Date | Wed, 22 Nov 2023 09:38:09 +0000 | From | "Russell King (Oracle)" <> | Subject | Re: [PATCH net-next v5 1/3] net: dsa: microchip: ksz8: Make flow control, speed, and duplex on CPU port configurable |
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On Wed, Nov 22, 2023 at 10:25:43AM +0100, Oleksij Rempel wrote: > Allow flow control, speed, and duplex settings on the CPU port to be > configurable. Previously, the speed and duplex relied on default switch > values, which limited flexibility. Additionally, flow control was > hardcoded and only functional in duplex mode. This update enhances the > configurability of these parameters. > > Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> > Reviewed-by: Simon Horman <simon.horman@corigine.com> > Reviewed-by: Vladimir Oltean <olteanv@gmail.com> > --- > drivers/net/dsa/microchip/ksz8.h | 4 ++ > drivers/net/dsa/microchip/ksz8795.c | 54 +++++++++++++++++++++++++- > drivers/net/dsa/microchip/ksz_common.c | 1 + > 3 files changed, 57 insertions(+), 2 deletions(-) > > diff --git a/drivers/net/dsa/microchip/ksz8.h b/drivers/net/dsa/microchip/ksz8.h > index ef653bbfde75..571c26ce71e4 100644 > --- a/drivers/net/dsa/microchip/ksz8.h > +++ b/drivers/net/dsa/microchip/ksz8.h > @@ -54,5 +54,9 @@ int ksz8_reset_switch(struct ksz_device *dev); > int ksz8_switch_init(struct ksz_device *dev); > void ksz8_switch_exit(struct ksz_device *dev); > int ksz8_change_mtu(struct ksz_device *dev, int port, int mtu); > +void ksz8_phylink_mac_link_up(struct ksz_device *dev, int port, > + unsigned int mode, phy_interface_t interface, > + struct phy_device *phydev, int speed, int duplex, > + bool tx_pause, bool rx_pause); > > #endif > diff --git a/drivers/net/dsa/microchip/ksz8795.c b/drivers/net/dsa/microchip/ksz8795.c > index 8deb217638d3..3504e7238eba 100644 > --- a/drivers/net/dsa/microchip/ksz8795.c > +++ b/drivers/net/dsa/microchip/ksz8795.c > @@ -1528,6 +1528,58 @@ void ksz8_config_cpu_port(struct dsa_switch *ds) > } > } > > +/** > + * ksz8_cpu_port_link_up - Configures the CPU port of the switch. > + * @dev: The KSZ device instance. > + * @speed: The desired link speed. > + * @duplex: The desired duplex mode. > + * @tx_pause: If true, enables transmit pause. > + * @rx_pause: If true, enables receive pause. > + * > + * Description: > + * The function configures flow control and speed settings for the CPU > + * port of the switch based on the desired settings, current duplex mode, and > + * speed. > + */ > +static void ksz8_cpu_port_link_up(struct ksz_device *dev, int speed, int duplex, > + bool tx_pause, bool rx_pause) > +{ > + const u16 *regs = dev->info->regs; > + u8 ctrl = 0; > + > + /* SW_FLOW_CTRL, SW_HALF_DUPLEX, and SW_10_MBIT bits are bootstrappable > + * at least on KSZ8873. They can have different values depending on your > + * board setup. > + */ > + if (duplex) { > + if (tx_pause || rx_pause) > + ctrl |= SW_FLOW_CTRL;
Please don't make this dependent on duplex, and allow phylink to enforce that. For example, phylink_resolve_an_pause() will only enable tx/rx pause if in full duplex mode.
> + } else { > + ctrl |= SW_HALF_DUPLEX; > + } > + > + /* This hardware only supports SPEED_10 and SPEED_100. For SPEED_10 > + * we need to set the SW_10_MBIT bit. Otherwise, we can leave it 0. > + */ > + if (speed == SPEED_10) > + ctrl |= SW_10_MBIT; > + > + ksz_rmw8(dev, regs[S_BROADCAST_CTRL], SW_HALF_DUPLEX | SW_FLOW_CTRL | > + SW_10_MBIT, ctrl);
So this is using SW_FLOW_CTRL with the S_BROADCAST_CTRL register...
> @@ -1576,8 +1628,6 @@ int ksz8_setup(struct dsa_switch *ds) > */ > ds->vlan_filtering_is_global = true; > > - ksz_cfg(dev, S_REPLACE_VID_CTRL, SW_FLOW_CTRL, true);
But previously it was being used with the S_REPLACE_VID_CTRL register. Doesn't make sense to me.
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