Messages in this thread | | | From | Fei Shao <> | Date | Thu, 23 Nov 2023 12:04:39 +0800 | Subject | Re: [PATCH v3 2/3] clk: mediatek: mt8195-topckgen: Refactor parents for top_dp/edp muxes |
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On Fri, Nov 3, 2023 at 6:25 PM AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> wrote: > > The top_dp and top_edp muxes can be both parented to either TVDPLL1 > or TVDPLL2, two identically specced PLLs for the specific purpose of > giving out pixel clock: this becomes a problem when the MediaTek > DisplayPort Interface (DPI) driver tries to set the pixel clock rate. > > In the usecase of two simultaneous outputs (using two controllers), > it was seen that one of the displays would sometimes display garbled > output (if any at all) and this was because: > - top_edp was set to TVDPLL1, outputting X GHz > - top_dp was set to TVDPLL2, outputting Y GHz > - mtk_dpi calls clk_set_rate(top_edp, Z GHz) > - top_dp is switched to TVDPLL1 > - TVDPLL1 changes its rate, top_edp outputs the wrong rate. > - eDP display is garbled > > To solve this issue, remove all TVDPLL1 parents from `top_dp` and > all TVDPLL2 parents from `top_edp`, plus, necessarily switch both > clocks to use the new MUX_GATE_CLR_SET_UPD_INDEXED() macro to be > able to use the right bit index for the new parents list. > > Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> > Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Fei Shao <fshao@chromium.org>
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