Messages in this thread | | | Date | Tue, 21 Nov 2023 10:59:16 +0100 (CET) | From | Geert Uytterhoeven <> | Subject | Re: [PATCH v3 1/9] clk: renesas: r9a08g045: Add IA55 pclk and its reset |
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Hi Claudiu,
On Mon, 20 Nov 2023, Claudiu wrote: > From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> > > IA55 interrupt controller is available on RZ/G3S SoC. Add IA55 pclk and > its reset. > > Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Thanks for your patch!
> --- a/drivers/clk/renesas/r9a08g045-cpg.c > +++ b/drivers/clk/renesas/r9a08g045-cpg.c > @@ -188,6 +188,7 @@ static const struct cpg_core_clk r9a08g045_core_clks[] __initconst = { > > static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = { > DEF_MOD("gic_gicclk", R9A08G045_GIC600_GICCLK, R9A08G045_CLK_P1, 0x514, 0), > + DEF_MOD("ia55_pclk", R9A08G045_IA55_PCLK, R9A08G045_CLK_P2, 0x518, 0),
This conflicts with [1], which you sent just before.
If that patch goes in first, I guess this new entry should gain ", MSTOP(PERI_CPU, BIT(13))", just like the entry for ia55_clk?
> DEF_MOD("ia55_clk", R9A08G045_IA55_CLK, R9A08G045_CLK_P1, 0x518, 1), > DEF_MOD("dmac_aclk", R9A08G045_DMAC_ACLK, R9A08G045_CLK_P3, 0x52c, 0), > DEF_MOD("sdhi0_imclk", R9A08G045_SDHI0_IMCLK, CLK_SD0_DIV4, 0x554, 0),
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
[1] "clk: renesas: rzg2l-cpg: Add support for MSTOP" https://lore.kernel.org/r/20231120070024.4079344-4-claudiu.beznea.uj@bp.renesas.com
Gr{oetje,eeting}s,
Geert
-- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
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