Messages in this thread | | | Subject | Re: [PATCH v2 0/8] Add support to handle misaligned accesses in S-mode | From | patchwork-bot+linux-riscv@kernel ... | Date | Thu, 02 Nov 2023 20:20:30 +0000 |
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Hello:
This series was applied to riscv/linux.git (for-next) by Palmer Dabbelt <palmer@rivosinc.com>:
On Wed, 4 Oct 2023 17:13:57 +0200 you wrote: > Since commit 61cadb9 ("Provide new description of misaligned load/store > behavior compatible with privileged architecture.") in the RISC-V ISA > manual, it is stated that misaligned load/store might not be supported. > However, the RISC-V kernel uABI describes that misaligned accesses are > supported. In order to support that, this series adds support for S-mode > handling of misaligned accesses as well support for prctl(PR_UNALIGN). > > [...]
Here is the summary with links: - [v2,1/8] riscv: remove unused functions in traps_misaligned.c https://git.kernel.org/riscv/c/f19c3b4239f5 - [v2,2/8] riscv: add support for misaligned trap handling in S-mode https://git.kernel.org/riscv/c/7c83232161f6 - [v2,3/8] riscv: report perf event for misaligned fault https://git.kernel.org/riscv/c/89c12fecdc4d - [v2,4/8] riscv: add floating point insn support to misaligned access emulation https://git.kernel.org/riscv/c/7c586a555a48 - [v2,5/8] riscv: add support for sysctl unaligned_enabled control https://git.kernel.org/riscv/c/bc38f61313d3 - [v2,6/8] riscv: annotate check_unaligned_access_boot_cpu() with __init https://git.kernel.org/riscv/c/90b11b470b2e - [v2,7/8] riscv: report misaligned accesses emulation to hwprobe https://git.kernel.org/riscv/c/71c54b3d169d - [v2,8/8] riscv: add support for PR_SET_UNALIGN and PR_GET_UNALIGN https://git.kernel.org/riscv/c/9f23a5d2f6b0
You are awesome, thank you! -- Deet-doot-dot, I am a bot. https://korg.docs.kernel.org/patchwork/pwbot.html
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