Messages in this thread | | | Date | Thu, 2 Nov 2023 12:08:48 +0100 | From | Borislav Petkov <> | Subject | Re: [PATCH 2/2] x86/barrier: Do not serialize MSR accesses on AMD |
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On Fri, Oct 27, 2023 at 09:09:05PM +0100, Andrew Cooper wrote: > Quoteth the APM (rev 3.41, June 2023): > > 16.11.2 WRMSR / RDMSR serialization for x2APIC Register > > The WRMSR instruction is used to write the APIC register set in x2APIC > mode. Normally WRMSR is > a serializing instruction, however when accessing x2APIC registers, the > serializing aspect of WRMSR > is relaxed to allow for more efficient access to those registers. > Consequently, a WRMSR write to an > x2APIC register may complete before older store operations are complete > and have become globally > visible. When strong ordering of an x2APIC write access is required with > respect to preceding memory > operations, software can insert a serializing instruction (such as > MFENCE) before the WRMSR > instruction. > > So which is right? This commit message, or the APM? (and yes, if > you're waiting on an APM update then the commit message should at least > note that one is coming.)
To clarify this one: there will be a CPUID bit which states that an MFENCE is not needed ATM and it'll be added to the APM. I'll add a note about it to the commit message too.
Thx.
-- Regards/Gruss, Boris.
https://people.kernel.org/tglx/notes-about-netiquette
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