Messages in this thread | | | Subject | Re: [PATCH net 6/7] net: hns3: fix VF reset fail issue | From | Paolo Abeni <> | Date | Thu, 02 Nov 2023 11:45:48 +0100 |
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On Sat, 2023-10-28 at 10:59 +0800, Jijie Shao wrote: > Currently the reset process in hns3 and firmware watchdog init process is > asynchronous. We think firmware watchdog initialization is completed > before VF clear the interrupt source. However, firmware initialization > may not complete early. So VF will receive multiple reset interrupts > and fail to reset. > > So we add delay before VF interrupt source and 5 ms delay > is enough to avoid second reset interrupt. > > Fixes: 427900d27d86 ("net: hns3: fix the timing issue of VF clearing interrupt sources") > Signed-off-by: Jijie Shao <shaojijie@huawei.com> > --- > .../ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c | 13 ++++++++++--- > 1 file changed, 10 insertions(+), 3 deletions(-) > > diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c > index 1c62e58ff6d8..7b87da031be6 100644 > --- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c > +++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c > @@ -1924,8 +1924,14 @@ static void hclgevf_service_task(struct work_struct *work) > hclgevf_mailbox_service_task(hdev); > } > > -static void hclgevf_clear_event_cause(struct hclgevf_dev *hdev, u32 regclr) > +static void hclgevf_clear_event_cause(struct hclgevf_dev *hdev, u32 regclr, > + bool need_dalay) > { > +#define HCLGEVF_RESET_DELAY 5 > + > + if (need_dalay) > + mdelay(HCLGEVF_RESET_DELAY);
5ms delay in an interrupt handler is quite a lot. What about scheduling a timer from the IH to clear the register when such delay is needed?
Thanks!
Paolo
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