Messages in this thread | | | Date | Fri, 17 Nov 2023 10:22:31 -0800 | Subject | Re: [PATCH net-next] net: microchip: lan743x : bidirectional throughput improvement | From | Florian Fainelli <> |
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On 11/15/23 21:43, Vishvambar Panth S wrote: > The LAN743x/PCI11xxx DMA descriptors are always 4 dwords long, but the > device supports placing the descriptors in memory back to back or > reserving space in between them using its DMA_DESCRIPTOR_SPACE (DSPACE) > configurable hardware setting. Currently DSPACE is unnecessarily set to > match the host's L1 cache line size, resulting in space reserved in > between descriptors in most platforms and causing a suboptimal behavior > (single PCIe Mem transaction per descriptor). By changing the setting > to DSPACE=16 many descriptors can be packed in a single PCIe Mem > transaction resulting in a massive performance improvement in > bidirectional tests without any negative effects. > Tested and verified improvements on x64 PC and several ARM platforms > (typical data below) > > Test setup 1: x64 PC with LAN7430 ---> x64 PC > > iperf3 UDP bidirectional with DSPACE set to L1 CACHE Size: > - - - - - - - - - - - - - - - - - - - - - - - - - > [ ID][Role] Interval Transfer Bitrate > [ 5][TX-C] 0.00-10.00 sec 170 MBytes 143 Mbits/sec sender > [ 5][TX-C] 0.00-10.04 sec 169 MBytes 141 Mbits/sec receiver > [ 7][RX-C] 0.00-10.00 sec 1.02 GBytes 876 Mbits/sec sender > [ 7][RX-C] 0.00-10.04 sec 1.02 GBytes 870 Mbits/sec receiver > > iperf3 UDP bidirectional with DSPACE set to 16 Bytes > - - - - - - - - - - - - - - - - - - - - - - - - - > [ ID][Role] Interval Transfer Bitrate > [ 5][TX-C] 0.00-10.00 sec 1.11 GBytes 956 Mbits/sec sender > [ 5][TX-C] 0.00-10.04 sec 1.11 GBytes 951 Mbits/sec receiver > [ 7][RX-C] 0.00-10.00 sec 1.10 GBytes 948 Mbits/sec sender > [ 7][RX-C] 0.00-10.04 sec 1.10 GBytes 942 Mbits/sec receiver > > Test setup 2 : RK3399 with LAN7430 ---> x64 PC > > RK3399 Spec: > The SOM-RK3399 is ARM module designed and developed by FriendlyElec. > Cores: 64-bit Dual Core Cortex-A72 + Quad Core Cortex-A53 > Frequency: Cortex-A72(up to 2.0GHz), Cortex-A53(up to 1.5GHz) > PCIe: PCIe x4, compatible with PCIe 2.1, Dual operation mode > > iperf3 UDP bidirectional with DSPACE set to L1 CACHE Size: > - - - - - - - - - - - - - - - - - - - - - - - - - > [ ID][Role] Interval Transfer Bitrate > [ 5][TX-C] 0.00-10.00 sec 534 MBytes 448 Mbits/sec sender > [ 5][TX-C] 0.00-10.05 sec 534 MBytes 446 Mbits/sec receiver > [ 7][RX-C] 0.00-10.00 sec 1.12 GBytes 961 Mbits/sec sender > [ 7][RX-C] 0.00-10.05 sec 1.11 GBytes 946 Mbits/sec receiver > > iperf3 UDP bidirectional with DSPACE set to 16 Bytes > - - - - - - - - - - - - - - - - - - - - - - - - - > [ ID][Role] Interval Transfer Bitrate > [ 5][TX-C] 0.00-10.00 sec 966 MBytes 810 Mbits/sec sender > [ 5][TX-C] 0.00-10.04 sec 965 MBytes 806 Mbits/sec receiver > [ 7][RX-C] 0.00-10.00 sec 1.11 GBytes 956 Mbits/sec sender > [ 7][RX-C] 0.00-10.04 sec 1.07 GBytes 919 Mbits/sec receiver > > Signed-off-by: Vishvambar Panth S <vishvambarpanth.s@microchip.com>
Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com> -- Florian
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