Messages in this thread | | | Date | Fri, 17 Nov 2023 09:11:41 -0400 | From | Jason Gunthorpe <> | Subject | Re: [PATCH 1/1] iommu/vt-d: Fix incorrect cache invalidation for mm notification |
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On Fri, Nov 17, 2023 at 05:09:33PM +0800, Lu Baolu wrote: > Commit 6bbd42e2df8f ("mmu_notifiers: call invalidate_range() when > invalidating TLBs") moved the secondary TLB invalidations into the TLB > invalidation functions to ensure that all secondary TLB invalidations > happen at the same time as the CPU invalidation and added a flush-all > type of secondary TLB invalidation for the batched mode, where a range > of [0, -1UL) is used to indicates that the range extends to the end of > the address space. > > However, using an end address of -1UL caused an overflow in the Intel > IOMMU driver, where the end address was rounded up to the next page. > As a result, both the IOTLB and device ATC were not invalidated correctly. > > Add a flush all helper function and call it when the invalidation range > is from 0 to -1UL, ensuring that the entire caches are invalidated > correctly. > > Fixes: 6bbd42e2df8f ("mmu_notifiers: call invalidate_range() when invalidating TLBs") > Cc: stable@vger.kernel.org > Cc: Huang Ying <ying.huang@intel.com> > Cc: Alistair Popple <apopple@nvidia.com> > Tested-by: Luo Yuzhang <yuzhang.luo@intel.com> # QAT > Tested-by: Tony Zhu <tony.zhu@intel.com> # DSA > Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com> > --- > drivers/iommu/intel/svm.c | 26 ++++++++++++++++++++++++++ > 1 file changed, 26 insertions(+)
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
This should go to -rc
Jason
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