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SubjectRe: [PATCH V12 16/23] mmc: sdhci-uhs2: add clock operations
On Tue, Oct 3, 2023 at 7:13 PM Ulf Hansson <ulf.hansson@linaro.org> wrote:
>
> On Fri, 15 Sept 2023 at 11:44, Victor Shih <victorshihgli@gmail.com> wrote:
> >
> > From: Victor Shih <victor.shih@genesyslogic.com.tw>
> >
> > This is a sdhci version of mmc's uhs2_[enable|disable]_clk operations.
> >
> > Signed-off-by: Ben Chuang <ben.chuang@genesyslogic.com.tw>
> > Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
> > Signed-off-by: Victor Shih <victor.shih@genesyslogic.com.tw>
> > Acked-by: Adrian Hunter <adrian.hunter@intel.com>
>
> The similar comments as posted for patch 15 applies to $subject patch
> too. Please have a look at those and fix these for the $subject patch
> too.
>

Hi, Ulf

I will merge patch#15, patch#16 and patch#17 into one patch(patch#15)
for version 13.

Thanks, Victor Shih

> > ---
> >
> > Updates in V8:
> > - Remove unnecessary include file.
> > - read_poll_timeout() to instead of read_poll_timeout_atomic()
> > in sdhci_uhs2_enable_clk().
> > - Put the comment on the end and put the lines in descending
> > line length in sdhci_uhs2_enable_clk().
> > - Modify return value in sdhci_uhs2_enable_clk().
> >
> > Updates in V6:
> > - Remove unnecessary functions.
> >
> > ---
> >
> > drivers/mmc/host/sdhci-uhs2.c | 30 ++++++++++++++++++++++++++++++
> > 1 file changed, 30 insertions(+)
> >
> > diff --git a/drivers/mmc/host/sdhci-uhs2.c b/drivers/mmc/host/sdhci-uhs2.c
> > index 4c2a56629ab3..af1b0c5e48fd 100644
> > --- a/drivers/mmc/host/sdhci-uhs2.c
> > +++ b/drivers/mmc/host/sdhci-uhs2.c
> > @@ -329,6 +329,36 @@ static int sdhci_uhs2_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
> > return 0;
> > }
> >
> > +static int sdhci_uhs2_disable_clk(struct mmc_host *mmc)
> > +{
> > + struct sdhci_host *host = mmc_priv(mmc);
> > + u16 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
> > +
> > + clk &= ~SDHCI_CLOCK_CARD_EN;
> > + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
> > +
> > + return 0;
> > +}
> > +
> > +static int sdhci_uhs2_enable_clk(struct mmc_host *mmc)
> > +{
> > + struct sdhci_host *host = mmc_priv(mmc);
> > + u16 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
> > + int timeout_us = 20000; /* 20ms */
> > + u32 val;
> > +
> > + clk |= SDHCI_CLOCK_CARD_EN;
> > + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
> > +
> > + if (read_poll_timeout(sdhci_readw, val, (val & SDHCI_CLOCK_INT_STABLE),
> > + 10, timeout_us, true, host, SDHCI_CLOCK_CONTROL)) {
> > + pr_err("%s: Internal clock never stabilised.\n", mmc_hostname(host->mmc));
> > + sdhci_dumpregs(host);
> > + return -EIO;
> > + }
> > + return 0;
> > +}
> > +
> > /*****************************************************************************\
> > * *
> > * Driver init/exit *
>
> Kind regards
> Uffe

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