Messages in this thread Patch in this message | | | From | Srinivas Goud <> | Subject | [PATCH v5 1/3] dt-bindings: can: xilinx_can: Add 'xlnx,has-ecc' optional property | Date | Fri, 17 Nov 2023 14:58:54 +0530 |
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ECC feature added to CAN TX_OL, TX_TL and RX FIFOs of Xilinx AXI CAN Controller. Part of this feature configuration and counter registers added in IP for 1bit/2bit ECC errors.
'xlnx,has-ecc' is optional property and added to Xilinx AXI CAN Controller node if ECC block enabled in the HW
Signed-off-by: Srinivas Goud <srinivas.goud@amd.com> --- Changes in v5: Update property description
Changes in v4: Fix binding check warning Update property description
Changes in v3: Update commit description Changes in v2: None
Documentation/devicetree/bindings/net/can/xilinx,can.yaml | 5 +++++ 1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/can/xilinx,can.yaml b/Documentation/devicetree/bindings/net/can/xilinx,can.yaml index 64d57c3..8d4e5af 100644 --- a/Documentation/devicetree/bindings/net/can/xilinx,can.yaml +++ b/Documentation/devicetree/bindings/net/can/xilinx,can.yaml @@ -49,6 +49,10 @@ properties: resets: maxItems: 1 + xlnx,has-ecc: + $ref: /schemas/types.yaml#/definitions/flag + description: CAN TX_OL, TX_TL and RX FIFOs have ECC support(AXI CAN) + required: - compatible - reg @@ -137,6 +141,7 @@ examples: interrupts = <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; + xlnx,has-ecc; }; - | -- 2.1.1
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