Messages in this thread | | | Date | Mon, 13 Nov 2023 18:35:43 +0200 | From | Andy Shevchenko <> | Subject | Re: [PATCH V7 2/3] pinctrl: Add support pin control for UP board CPLD/FPGA |
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On Mon, Nov 13, 2023 at 03:15:58PM +0100, Linus Walleij wrote: > Hi Larry, Andy, > > On Tue, Oct 31, 2023 at 2:51 AM larry.lai <larry.lai@yunjingtech.com> wrote: > > > The UP Squared board <http://www.upboard.com> implements certain > > features (pin control) through an on-board FPGA. > > > > Reported-by: kernel test robot <lkp@intel.com>
It may not be reported as it's brand new code.
> > Signed-off-by: Gary Wang <garywang@aaeon.com.tw> > > Signed-off-by: larry.lai <larry.lai@yunjingtech.com>
(...)
> > +#include "core.h" > > +#include "intel/pinctrl-intel.h"
> As mentioned this is using the intel core pin control driver infrastructure > so I want Andy's ACK on this before I merge it.
I'm pretty much sure it's an abuse of that.
I guess I told this already in the previous rounds of review... I'll try to find time to look at this, but it looks like it still needs some job before being taken.
-- With Best Regards, Andy Shevchenko
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