Messages in this thread Patch in this message | | | Date | Sun, 12 Nov 2023 13:08:20 +0300 | Subject | Re: [PATCH v1] mtd: rawnand: meson: initialize clock register | From | Arseniy Krasnov <> |
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On 09.11.2023 08:40, Arseniy Krasnov wrote: > Clock register must be also initialized during controller probing. If > this is not performed (for example by bootloader before) - controller > will not work. > > Signed-off-by: Arseniy Krasnov <avkrasnov@salutedevices.com> > --- > drivers/mtd/nand/raw/meson_nand.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/drivers/mtd/nand/raw/meson_nand.c b/drivers/mtd/nand/raw/meson_nand.c > index 0d4d358152d7..4e7fa943928c 100644 > --- a/drivers/mtd/nand/raw/meson_nand.c > +++ b/drivers/mtd/nand/raw/meson_nand.c > @@ -91,6 +91,8 @@ > > /* eMMC clock register, misc control */ > #define CLK_SELECT_NAND BIT(31) > +#define CLK_ALWAYS_ON_NAND BIT(24) > +#define CLK_ENABLE_VALUE 0x245 ^^^^^^
Hi,
@Liang, it will be great, if You'll give some details about this magic value. I get it from vendor's driver and it makes NAND controller alive, but I don't have any docs.
Thanks, Arseniy
> > #define NFC_CLK_CYCLE 6 > > @@ -1152,7 +1154,7 @@ static int meson_nfc_clk_init(struct meson_nfc *nfc) > return PTR_ERR(nfc->nand_clk); > > /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */ > - writel(CLK_SELECT_NAND | readl(nfc->reg_clk), > + writel(CLK_ALWAYS_ON_NAND | CLK_SELECT_NAND | CLK_ENABLE_VALUE, > nfc->reg_clk); > > ret = clk_prepare_enable(nfc->core_clk);
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