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    Subject[PATCH v13 08/10] arm64: dts: qcom: sc8280xp: Add multiport controller node for SC8280
    Date
    Add USB and DWC3 node for tertiary port of SC8280 along with multiport
    IRQ's and phy's. This will be used as a base for SA8295P and SA8295-Ride
    platforms.

    Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
    ---
    arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 84 ++++++++++++++++++++++++++
    1 file changed, 84 insertions(+)

    diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
    index cad59af7ccef..5f64f75b07db 100644
    --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
    +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
    @@ -3330,6 +3330,90 @@ system-cache-controller@9200000 {
    interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
    };

    + usb_2: usb@a4f8800 {
    + compatible = "qcom,sc8280xp-dwc3-mp", "qcom,dwc3";
    + reg = <0 0x0a4f8800 0 0x400>;
    + #address-cells = <2>;
    + #size-cells = <2>;
    + ranges;
    +
    + clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>,
    + <&gcc GCC_USB30_MP_MASTER_CLK>,
    + <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>,
    + <&gcc GCC_USB30_MP_SLEEP_CLK>,
    + <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
    + <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
    + <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>,
    + <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>,
    + <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
    + clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi",
    + "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys";
    +
    + assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
    + <&gcc GCC_USB30_MP_MASTER_CLK>;
    + assigned-clock-rates = <19200000>, <200000000>;
    +
    + interrupts-extended = <&pdc 127 IRQ_TYPE_EDGE_RISING>,
    + <&pdc 126 IRQ_TYPE_EDGE_RISING>,
    + <&pdc 129 IRQ_TYPE_EDGE_RISING>,
    + <&pdc 128 IRQ_TYPE_EDGE_RISING>,
    + <&pdc 131 IRQ_TYPE_EDGE_RISING>,
    + <&pdc 130 IRQ_TYPE_EDGE_RISING>,
    + <&pdc 133 IRQ_TYPE_EDGE_RISING>,
    + <&pdc 132 IRQ_TYPE_EDGE_RISING>,
    + <&pdc 16 IRQ_TYPE_LEVEL_HIGH>,
    + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
    + <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
    + <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
    + <&intc GIC_SPI 857 IRQ_TYPE_LEVEL_HIGH>,
    + <&intc GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>;
    +
    + interrupt-names = "dp_hs_phy_1", "dm_hs_phy_1",
    + "dp_hs_phy_2", "dm_hs_phy_2",
    + "dp_hs_phy_3", "dm_hs_phy_3",
    + "dp_hs_phy_4", "dm_hs_phy_4",
    + "ss_phy_1", "ss_phy_2",
    + "pwr_event_1",
    + "pwr_event_2",
    + "pwr_event_3",
    + "pwr_event_4";
    +
    + power-domains = <&gcc USB30_MP_GDSC>;
    + required-opps = <&rpmhpd_opp_nom>;
    +
    + resets = <&gcc GCC_USB30_MP_BCR>;
    +
    + interconnects = <&aggre1_noc MASTER_USB3_MP 0 &mc_virt SLAVE_EBI1 0>,
    + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_MP 0>;
    + interconnect-names = "usb-ddr", "apps-usb";
    +
    + wakeup-source;
    +
    + status = "disabled";
    +
    + usb_2_dwc3: usb@a400000 {
    + compatible = "snps,dwc3";
    + reg = <0 0x0a400000 0 0xcd00>;
    + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
    + iommus = <&apps_smmu 0x800 0x0>;
    + phys = <&usb_2_hsphy0>, <&usb_2_qmpphy0>,
    + <&usb_2_hsphy1>, <&usb_2_qmpphy1>,
    + <&usb_2_hsphy2>,
    + <&usb_2_hsphy3>;
    + phy-names = "usb2-port0", "usb3-port0",
    + "usb2-port1", "usb3-port1",
    + "usb2-port2",
    + "usb2-port3";
    +
    + /*
    + * Multiport controllers are host only contollers, so
    + * the dr_mode can be defaulted to host irrespective of
    + * the platform.
    + */
    + dr_mode = "host";
    + };
    + };
    +
    usb_0: usb@a6f8800 {
    compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3";
    reg = <0 0x0a6f8800 0 0x400>;
    --
    2.42.0
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