Messages in this thread | | | From | David Laight <> | Subject | RE: [PATCH 0/7] Add support to handle misaligned accesses in S-mode | Date | Wed, 4 Oct 2023 08:26:49 +0000 |
| |
From: Clément Léger > Sent: 02 October 2023 08:40 > > On 30/09/2023 11:23, Conor Dooley wrote: > > On Tue, Sep 26, 2023 at 05:03:09PM +0200, Clément Léger wrote: > >> Since commit 61cadb9 ("Provide new description of misaligned load/store > >> behavior compatible with privileged architecture.") in the RISC-V ISA > >> manual, it is stated that misaligned load/store might not be supported. > >> However, the RISC-V kernel uABI describes that misaligned accesses are > >> supported. ...
That it just really horrid. If the cpu is going to trap misaligned accesses then you want The compiler generated code (ie packed data) not to generate misaligned accesses. So you have to change the kernel uABI.
OTOH if you known that such accesses won't fault and will be not really slower than aligned accesses then optimised versions of some functions (like memcpy and checksums) can use misaligned accesses.
David
- Registered Address Lakeside, Bramley Road, Mount Farm, Milton Keynes, MK1 1PT, UK Registration No: 1397386 (Wales)
| |