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    Subject[PATCH v10 20/20] riscv: dts: starfive: add PCIe dts configuration for JH7110
    Date
    Add PCIe dts configuraion for JH7110 SoC platform.

    Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
    Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
    ---
    .../jh7110-starfive-visionfive-2.dtsi | 64 ++++++++++++++
    arch/riscv/boot/dts/starfive/jh7110.dtsi | 86 +++++++++++++++++++
    2 files changed, 150 insertions(+)

    diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
    index 2c02358abd71..2124539f415d 100644
    --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
    +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
    @@ -232,6 +232,22 @@
    status = "okay";
    };

    +&pcie0 {
    + perst-gpios = <&sysgpio 26 GPIO_ACTIVE_LOW>;
    + phys = <&pciephy0>;
    + pinctrl-names = "default";
    + pinctrl-0 = <&pcie0_pins>;
    + status = "okay";
    +};
    +
    +&pcie1 {
    + perst-gpios = <&sysgpio 28 GPIO_ACTIVE_LOW>;
    + phys = <&pciephy1>;
    + pinctrl-names = "default";
    + pinctrl-0 = <&pcie1_pins>;
    + status = "okay";
    +};
    +
    &qspi {
    #address-cells = <1>;
    #size-cells = <0>;
    @@ -402,6 +418,54 @@
    };
    };

    + pcie0_pins: pcie0-0 {
    + clkreq-pins {
    + pinmux = <GPIOMUX(27, GPOUT_LOW,
    + GPOEN_DISABLE,
    + GPI_NONE)>;
    + bias-pull-down;
    + drive-strength = <2>;
    + input-enable;
    + input-schmitt-disable;
    + slew-rate = <0>;
    + };
    +
    + wake-pins {
    + pinmux = <GPIOMUX(32, GPOUT_LOW,
    + GPOEN_DISABLE,
    + GPI_NONE)>;
    + bias-pull-up;
    + drive-strength = <2>;
    + input-enable;
    + input-schmitt-disable;
    + slew-rate = <0>;
    + };
    + };
    +
    + pcie1_pins: pcie1-0 {
    + clkreq-pins {
    + pinmux = <GPIOMUX(29, GPOUT_LOW,
    + GPOEN_DISABLE,
    + GPI_NONE)>;
    + bias-pull-down;
    + drive-strength = <2>;
    + input-enable;
    + input-schmitt-disable;
    + slew-rate = <0>;
    + };
    +
    + wake-pins {
    + pinmux = <GPIOMUX(21, GPOUT_LOW,
    + GPOEN_DISABLE,
    + GPI_NONE)>;
    + bias-pull-up;
    + drive-strength = <2>;
    + input-enable;
    + input-schmitt-disable;
    + slew-rate = <0>;
    + };
    + };
    +
    spi0_pins: spi0-0 {
    mosi-pins {
    pinmux = <GPIOMUX(52, GPOUT_SYS_SPI0_TXD,
    diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
    index e85464c328d0..1a1e97287c5e 100644
    --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
    +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
    @@ -1045,5 +1045,91 @@
    #reset-cells = <1>;
    power-domains = <&pwrc JH7110_PD_VOUT>;
    };
    +
    + pcie0: pcie@940000000 {
    + compatible = "starfive,jh7110-pcie";
    + reg = <0x9 0x40000000 0x0 0x1000000>,
    + <0x0 0x2b000000 0x0 0x100000>;
    + reg-names = "cfg", "apb";
    + linux,pci-domain = <0>;
    + #address-cells = <3>;
    + #size-cells = <2>;
    + #interrupt-cells = <1>;
    + ranges = <0x82000000 0x0 0x30000000 0x0 0x30000000 0x0 0x08000000>,
    + <0xc3000000 0x9 0x00000000 0x9 0x00000000 0x0 0x40000000>;
    + interrupts = <56>;
    + interrupt-map-mask = <0x0 0x0 0x0 0x7>;
    + interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc0 0x1>,
    + <0x0 0x0 0x0 0x2 &pcie_intc0 0x2>,
    + <0x0 0x0 0x0 0x3 &pcie_intc0 0x3>,
    + <0x0 0x0 0x0 0x4 &pcie_intc0 0x4>;
    + msi-controller;
    + device_type = "pci";
    + starfive,stg-syscon = <&stg_syscon>;
    + bus-range = <0x0 0xff>;
    + clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>,
    + <&stgcrg JH7110_STGCLK_PCIE0_TL>,
    + <&stgcrg JH7110_STGCLK_PCIE0_AXI_MST0>,
    + <&stgcrg JH7110_STGCLK_PCIE0_APB>;
    + clock-names = "noc", "tl", "axi_mst0", "apb";
    + resets = <&stgcrg JH7110_STGRST_PCIE0_AXI_MST0>,
    + <&stgcrg JH7110_STGRST_PCIE0_AXI_SLV0>,
    + <&stgcrg JH7110_STGRST_PCIE0_AXI_SLV>,
    + <&stgcrg JH7110_STGRST_PCIE0_BRG>,
    + <&stgcrg JH7110_STGRST_PCIE0_CORE>,
    + <&stgcrg JH7110_STGRST_PCIE0_APB>;
    + reset-names = "mst0", "slv0", "slv", "brg",
    + "core", "apb";
    + status = "disabled";
    +
    + pcie_intc0: interrupt-controller {
    + #address-cells = <0>;
    + #interrupt-cells = <1>;
    + interrupt-controller;
    + };
    + };
    +
    + pcie1: pcie@9c0000000 {
    + compatible = "starfive,jh7110-pcie";
    + reg = <0x9 0xc0000000 0x0 0x1000000>,
    + <0x0 0x2c000000 0x0 0x100000>;
    + reg-names = "cfg", "apb";
    + linux,pci-domain = <1>;
    + #address-cells = <3>;
    + #size-cells = <2>;
    + #interrupt-cells = <1>;
    + ranges = <0x82000000 0x0 0x38000000 0x0 0x38000000 0x0 0x08000000>,
    + <0xc3000000 0x9 0x80000000 0x9 0x80000000 0x0 0x40000000>;
    + interrupts = <57>;
    + interrupt-map-mask = <0x0 0x0 0x0 0x7>;
    + interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc1 0x1>,
    + <0x0 0x0 0x0 0x2 &pcie_intc1 0x2>,
    + <0x0 0x0 0x0 0x3 &pcie_intc1 0x3>,
    + <0x0 0x0 0x0 0x4 &pcie_intc1 0x4>;
    + msi-controller;
    + device_type = "pci";
    + starfive,stg-syscon = <&stg_syscon>;
    + bus-range = <0x0 0xff>;
    + clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>,
    + <&stgcrg JH7110_STGCLK_PCIE1_TL>,
    + <&stgcrg JH7110_STGCLK_PCIE1_AXI_MST0>,
    + <&stgcrg JH7110_STGCLK_PCIE1_APB>;
    + clock-names = "noc", "tl", "axi_mst0", "apb";
    + resets = <&stgcrg JH7110_STGRST_PCIE1_AXI_MST0>,
    + <&stgcrg JH7110_STGRST_PCIE1_AXI_SLV0>,
    + <&stgcrg JH7110_STGRST_PCIE1_AXI_SLV>,
    + <&stgcrg JH7110_STGRST_PCIE1_BRG>,
    + <&stgcrg JH7110_STGRST_PCIE1_CORE>,
    + <&stgcrg JH7110_STGRST_PCIE1_APB>;
    + reset-names = "mst0", "slv0", "slv", "brg",
    + "core", "apb";
    + status = "disabled";
    +
    + pcie_intc1: interrupt-controller {
    + #address-cells = <0>;
    + #interrupt-cells = <1>;
    + interrupt-controller;
    + };
    + };
    };
    };
    --
    2.17.1
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