Messages in this thread | | | Date | Mon, 30 Oct 2023 09:00:04 -0700 | Subject | Re: [PATCH v1 2/2] dmaengine: idxd: Fix the incorrect descriptions | From | Dave Jiang <> |
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On 10/29/23 01:00, 'Guanjun' wrote: > From: Guanjun <guanjun@linux.alibaba.com> > > Fix the incorrect descriptions for the GRPCFG register. > No functional changes > > Signed-off-by: Guanjun <guanjun@linux.alibaba.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Thanks!
> --- > drivers/dma/idxd/registers.h | 13 ++++++++----- > 1 file changed, 8 insertions(+), 5 deletions(-) > > diff --git a/drivers/dma/idxd/registers.h b/drivers/dma/idxd/registers.h > index 7b54a3939ea1..385a162a55f2 100644 > --- a/drivers/dma/idxd/registers.h > +++ b/drivers/dma/idxd/registers.h > @@ -440,12 +440,15 @@ union wqcfg { > /* > * This macro calculates the offset into the GRPCFG register > * idxd - struct idxd * > - * n - wq id > - * ofs - the index of the 32b dword for the config register > + * n - group id > + * ofs - the index of the 64b qword for the config register > * > - * The WQCFG register block is divided into groups per each wq. The n index > - * allows us to move to the register group that's for that particular wq. > - * Each register is 32bits. The ofs gives us the number of register to access. > + * The GRPCFG register block is divided into three different types, that > + * includes GRPWQCFG, GRPENGCFG and GRPFLGCFG. The n index in each group > + * allows us to move to the register group that's for that particular wq, > + * engine or group flag. > + * Each register is 64bits. And the ofs in GRPWQCFG gives us the number > + * of register to access. > */ > #define GRPWQCFG_OFFSET(idxd_dev, n, ofs) ((idxd_dev)->grpcfg_offset +\ > (n) * GRPCFG_SIZE + sizeof(u64) * (ofs))
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