Messages in this thread | | | Subject | Re: [PATCH v6 0/4] riscv: tlb flush improvements | From | Nadav Amit <> | Date | Mon, 30 Oct 2023 16:01:48 +0200 |
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> On Oct 30, 2023, at 3:30 PM, Alexandre Ghiti <alexghiti@rivosinc.com> wrote: > > + on_each_cpu_mask(cmask, > + __ipi_flush_tlb_range_asid, > + &ftd, 1); >
Unrelated, but having fed on the stack might cause it to be unaligned to the cacheline, which in x86 we have seen introduces some overhead.
Actually, it is best not to put it on the stack, if possible to reduce cache traffic.
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