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SubjectRe: [PATCH v2 0/4] pinctrl: qcom: Introduce Pinctrl/GPIO for SM8650
Hi,

On 30/10/2023 10:50, Neil Armstrong wrote:
> The SM8650 Top Level Mode Multiplexer supports 211 GPIOs,
> and the usual UFS Reset, SDC Clk/Cmd/Data special pins.
>
> An handful of pins can have their IRQ generated by the PDC
> module, and for this support for the new wakeup_present &
> wakeup_enable_bit is required to allow the "wakeup" event
> to be passed to PDC and generate an interrupt or a wakeup
> system event.
>
> As SM8550, it also supports the i2c_pull_bit bit to enable the
> on-SoC load resistor for I2C busses.
>
> Dependencies: None
>
> For convenience, a regularly refreshed linux-next based git tree containing
> all the SM8650 related work is available at:
> https://git.codelinaro.org/neil.armstrong/linux/-/tree/topic/sm8650/upstream/integ
>
> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
> ---
> Changes in v2:
> - Collect reviewed-bys
> - Fixed unevaluatedProperties handling, and dropped the true properties
> - Link to v1: https://lore.kernel.org/r/20231025-topic-sm8650-upstream-tlmm-v1-0-4e3d84a3a46b@linaro.org
>
> ---
> Neil Armstrong (4):
> dt-bindings: pinctrl: document the SM8650 Top Level Mode Multiplexer
> pinctrl: qcom: handle intr_target_reg wakeup_present/enable bits
> pinctrl: qcom: Introduce the SM8650 Top Level Mode Multiplexer driver
> fixup! pinctrl: qcom: handle intr_target_reg wakeup_present/enable bits

Please ignore this patchset, I forgot to squash patch 4....

Neil

>
> .../bindings/pinctrl/qcom,sm8650-tlmm.yaml | 147 ++
> drivers/pinctrl/qcom/Kconfig.msm | 8 +
> drivers/pinctrl/qcom/Makefile | 1 +
> drivers/pinctrl/qcom/pinctrl-msm.c | 42 +
> drivers/pinctrl/qcom/pinctrl-msm.h | 5 +
> drivers/pinctrl/qcom/pinctrl-sm8650.c | 1762 ++++++++++++++++++++
> 6 files changed, 1965 insertions(+)
> ---
> base-commit: ed75ce58b3a55d2cd95b68a06fdb010e1e18d825
> change-id: 20231016-topic-sm8650-upstream-tlmm-4ece354ef319
>
> Best regards,

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