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    SubjectRe: [PATCH 4/6] PCI: qcom: Add support for IPQ5018
    On Tue, 3 Oct 2023 at 15:10, Nitheesh Sekar <quic_nsekar@quicinc.com> wrote:
    >
    > Added a new compatible 'qcom,pcie-ipq5018' and modified
    > get_resources of 'ops 2_9_0' to get the clocks from the
    > device-tree.
    >
    > Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
    > Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
    > Co-developed-by: Devi Priya <quic_devipriy@quicinc.com>
    > Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
    > Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com>
    > ---
    > drivers/pci/controller/dwc/pcie-qcom.c | 22 ++++++++--------------
    > 1 file changed, 8 insertions(+), 14 deletions(-)
    >
    > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
    > index e2f29404c84e..bb0717190920 100644
    > --- a/drivers/pci/controller/dwc/pcie-qcom.c
    > +++ b/drivers/pci/controller/dwc/pcie-qcom.c
    > @@ -197,10 +197,10 @@ struct qcom_pcie_resources_2_7_0 {
    > struct reset_control *rst;
    > };
    >
    > -#define QCOM_PCIE_2_9_0_MAX_CLOCKS 5
    > struct qcom_pcie_resources_2_9_0 {
    > - struct clk_bulk_data clks[QCOM_PCIE_2_9_0_MAX_CLOCKS];
    > + struct clk_bulk_data *clks;
    > struct reset_control *rst;
    > + int num_clks;
    > };
    >
    > union qcom_pcie_resources {
    > @@ -1048,17 +1048,10 @@ static int qcom_pcie_get_resources_2_9_0(struct qcom_pcie *pcie)
    > struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0;
    > struct dw_pcie *pci = pcie->pci;
    > struct device *dev = pci->dev;
    > - int ret;
    >
    > - res->clks[0].id = "iface";
    > - res->clks[1].id = "axi_m";
    > - res->clks[2].id = "axi_s";
    > - res->clks[3].id = "axi_bridge";
    > - res->clks[4].id = "rchng";
    > -
    > - ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks);

    Changing this to devm_clk_bulk_get_optional would be easier and will
    follow the design of the driver.

    > - if (ret < 0)
    > - return ret;
    > + res->num_clks = devm_clk_bulk_get_all(dev, &res->clks);
    > + if (res->num_clks < 0)
    > + return res->num_clks;
    >
    > res->rst = devm_reset_control_array_get_exclusive(dev);
    > if (IS_ERR(res->rst))
    > @@ -1071,7 +1064,7 @@ static void qcom_pcie_deinit_2_9_0(struct qcom_pcie *pcie)
    > {
    > struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0;
    >
    > - clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks);
    > + clk_bulk_disable_unprepare(res->num_clks, res->clks);
    > }
    >
    > static int qcom_pcie_init_2_9_0(struct qcom_pcie *pcie)
    > @@ -1100,7 +1093,7 @@ static int qcom_pcie_init_2_9_0(struct qcom_pcie *pcie)
    >
    > usleep_range(2000, 2500);
    >
    > - return clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks);
    > + return clk_bulk_prepare_enable(res->num_clks, res->clks);
    > }
    >
    > static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie)
    > @@ -1605,6 +1598,7 @@ static const struct of_device_id qcom_pcie_match[] = {
    > { .compatible = "qcom,pcie-apq8064", .data = &cfg_2_1_0 },
    > { .compatible = "qcom,pcie-apq8084", .data = &cfg_1_0_0 },
    > { .compatible = "qcom,pcie-ipq4019", .data = &cfg_2_4_0 },
    > + { .compatible = "qcom,pcie-ipq5018", .data = &cfg_2_9_0 },
    > { .compatible = "qcom,pcie-ipq6018", .data = &cfg_2_9_0 },
    > { .compatible = "qcom,pcie-ipq8064", .data = &cfg_2_1_0 },
    > { .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 },
    > --
    > 2.17.1
    >


    --
    With best wishes
    Dmitry

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