Messages in this thread | | | Date | Tue, 3 Oct 2023 12:27:33 +0200 | From | Peter Zijlstra <> | Subject | Re: [RESEND PATCH V3 1/6] perf: Add branch stack extra |
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On Mon, Oct 02, 2023 at 08:57:57PM -0400, Liang, Kan wrote:
> > Did I already say that the ISE document raises more questions than it > > provides answers? > > Yes. Would an improved CPUID enumeration can address the questions? For > example, the CPUID enumeration can give the maximum number of counters > and supported width? I think we can discuss it with the architect.
So.. no. Suppose another arch goes and does the same, but with a different number and width of counters. They won't have CPUID.
I'm thinking we should do something like expose branch_counter_nr and branch_counter_width in the sysfs node, and then rename this extra field to counters.
Then userspace can do something like:
for (i = 0; i < branch_counter_nr; i++) { counter[i] = counters & ((1 << branch_counter_width) - 1); counters >>= branch_counter_width; }
to extract the actual counter values.
So then we end up with:
* { u64 nr; * { u64 hw_idx; } && PERF_SAMPLE_BRANCH_HW_INDEX * { u64 from, to, flags } lbr[nr]; + * { u64 counters; } cntr[nr] && PERF_SAMPLE_BRANCH_COUNTERS * } && PERF_SAMPLE_BRANCH_STACK
Have it explicitly named counters, have only the one flag and have sysfs files describe how to decode it.
Then for this Intel thing we have 4 counters of 2 bits, but if someone else were to do something different (both Power and ARM64 have this branch stack stuff now) they can describe it.
It is a bit wasteful on bits... but at least its clear I suppose.
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