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SubjectRe: [PATCH 06/10] clk: qcom: add the SM8650 Global Clock Controller driver
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On 10/25/23 09:32, Neil Armstrong wrote:
> Add Global Clock Controller (GCC) support for SM8650 platform.
>
> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
> ---
Just a couple remarks

1. looks like there's no usage of shared ops (corresponding
to enable_safe_parent or something along these lines
downstream)

2. none of the GDSCs have interesting flags.. I have this
little cheat sheet that you may find handy:

qcom,retain-regs -> RETAIN_FF_ENABLE
qcom,support-hw-trigger + set_mode in driver -> HW_CONTROL
qcom,no-status-check-on-disable -> VOTABLE
qcom,reset-aon-logic -> AON_RESET
domain-addr = clamp_io_ctrl

3. gcc_cpuss_ubwcp_clk_src uses the XO_A clock as parent, but
it's not there in the ftbl.. Could you confirm whether this
clock should even be accessed from HLOS?

[...]

> +static int gcc_sm8650_probe(struct platform_device *pdev)
> +{
> + struct regmap *regmap;
> + int ret;
> +
> + regmap = qcom_cc_map(pdev, &gcc_sm8650_desc);
> + if (IS_ERR(regmap))
> + return PTR_ERR(regmap);
> +
> + ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
> + ARRAY_SIZE(gcc_dfs_clocks));
> + if (ret)
> + return ret;
> +
> + /*
> + * Keep the critical clock always-On
> + * gcc_camera_ahb_clk, gcc_camera_xo_clk, gcc_disp_ahb_clk,
> + * gcc_disp_xo_clk, gcc_gpu_cfg_ahb_clk, gcc_video_ahb_clk,
> + * gcc_video_xo_clk
> + */
Could you make these comments inline, i.e.

regmap_update_bits(regmap, 0x26004, BIT(0), BIT(0)); /* gcc_camera_ahb_clk */

?

Konrad

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