Messages in this thread | | | Date | Tue, 24 Oct 2023 11:12:45 +0200 | Subject | Re: [PATCH 14/18] drm/mediatek: dpi: add support for dpi clock | From | AngeloGioacchino Del Regno <> |
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Il 23/10/23 16:40, amergnat@baylibre.com ha scritto: > From: Fabien Parent <fparent@baylibre.com> > > MT8365 requires an additional clock for DPI. Add support for that > additional clock. > > Signed-off-by: Fabien Parent <fparent@baylibre.com> > Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>
I'm not convinced that this is right... at all.
From a fast check of the MT8365 DPI clocks, I can see that the DPI0 clock declares parent VPLL_DPIX (a fixed clock), but nothing ever has VPLL_DPIX_EN (which is the GATE clock, enabling output of DPIx VPLL?).
But then, there's even more: no clock ever references the CLK_TOP_DPI0_SEL nor the CLK_TOP_DPI1_SEL gate, which is a PLL parent selector... in other platforms, that is muxing through the TVDPLL, but on MT8365 that is LVDSPLL?!
I have many questions now: * Two PLLs are apparently brought up, but which one is the right one?! * Is the LVDS PLL really used for DisplayPort? (dpi0_sel) * Is the VPLL_DPIx PLL used for DisplayPort instead? (dpi0_dpi0) * Why is the LVDSTX_PXL clock using the same PLL as DPI0?! * Why is the VPLL_DPIx gate never enabled? * Are you sure that CLK_MM_DPI0_DPI0's parent shouldn't be dpi0_sel instead? * Where is DPI1 in this SoC? Why is there a dpi1_sel clock, but no MM clock for the DPI1 controller? Is there any DPI1 controller, even?! * Why is there a DPI1 MUX, if there's no DPI1 controller?!
Answering all those questions will lead you to the right change, which I believe to be in the clock drivers, not here in mtk_dpi.c.
Cheers! Angelo
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