Messages in this thread Patch in this message | | | From | Dapeng Mi <> | Subject | [kvm-unit-tests Patch 2/5] x86: pmu: Change the minimum value of llc_misses event to 0 | Date | Tue, 24 Oct 2023 15:57:45 +0800 |
| |
Along with the CPU HW's upgrade and optimization, the count of LLC misses event for running loop() helper could be 0 just like seen on Sapphire Rapids.
So modify the lower limit of possible count range for LLC misses events to 0 to avoid LLC misses event test failure on Sapphire Rapids.
Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com> --- x86/pmu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/x86/pmu.c b/x86/pmu.c index 0def28695c70..7443fdab5c8a 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -35,7 +35,7 @@ struct pmu_event { {"instructions", 0x00c0, 10*N, 10.2*N}, {"ref cycles", 0x013c, 1*N, 30*N}, {"llc references", 0x4f2e, 1, 2*N}, - {"llc misses", 0x412e, 1, 1*N}, + {"llc misses", 0x412e, 0, 1*N}, {"branches", 0x00c4, 1*N, 1.1*N}, {"branch misses", 0x00c5, 0, 0.1*N}, }, amd_gp_events[] = { -- 2.34.1
| |