Messages in this thread | | | From | Geert Uytterhoeven <> | Date | Fri, 20 Oct 2023 09:32:45 +0200 | Subject | Re: [PATCH v2 09/10] riscv: dts: renesas: Add Andes PMU extension |
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Hi Peter,
On Thu, Oct 19, 2023 at 4:05 PM Yu Chien Peter Lin <peterlin@andestech.com> wrote: > Add "xandespmu" to ISA extensions, the SBI PMU driver will > probe the extension and use the non-standard irq source. > > Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> > --- > Changes v1 -> v2: > - New patch
Thanks for your patch!
> --- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi > +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi > @@ -26,7 +26,7 @@ cpu0: cpu@0 { > riscv,isa = "rv64imafdc"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", > - "zifencei", "zihpm"; > + "zifencei", "zihpm", "xandespmu"; > mmu-type = "riscv,sv39"; > i-cache-size = <0x8000>; > i-cache-line-size = <0x40>;
This extension is not documented in Documentation/devicetree/bindings/riscv/extensions.yaml. Perhaps it was introduced in an earlier patch in the series, to which I was not CCed?
Threading is broken, so I can't easily find the whole series in lore: https://lore.kernel.org/all/20231019140232.3660375-1-peterlin@andestech.com/
Gr{oetje,eeting}s,
Geert
-- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
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