Messages in this thread | | | Date | Mon, 2 Oct 2023 15:16:32 +0200 | From | Neil Armstrong <> | Subject | Re: [PATCH v4 1/2] irqchip/qcom-pdc: Add support for v3.2 HW |
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Hi Thomas,
On 02/10/2023 14:59, Thomas Gleixner wrote: > On Tue, Sep 05 2023 at 15:19, Neil Armstrong wrote: >> Starting from HW version 3.2 the IRQ_ENABLE bit has moved to the >> IRQ_i_CFG register and requires a change of the driver to avoid >> writing into an undefined register address. >> >> Get the HW version from registers and set the IRQ_ENABLE bit to the >> correct register depending on the HW version. >> >> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> >> Reviewed-by: Maulik Shah <quic_mkshah@quicinc.com> >> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> > > This S-O-B chain is broken. Who is the real author of that?
I'm the initial author, I sent a fixed version with cleaned-up S-o-b chain: https://lore.kernel.org/all/20230929-topic-sm8x50-upstream-pdc-ver-v5-0-800111572104@linaro.org /
Neil
> > https://www.kernel.org/doc/html/latest/process/submitting-patches.html#when-to-use-acked-by-cc-and-co-developed-by > > Thanks, > > tglx > >
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