Messages in this thread | | | Date | Wed, 18 Oct 2023 20:16:06 +0000 | From | Oliver Upton <> | Subject | Re: [PATCH] arm64: Independently update HDFGRTR_EL2 and HDFGWTR_EL2 |
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On Wed, Oct 18, 2023 at 01:40:37PM +0100, Marc Zyngier wrote: > On Wed, 18 Oct 2023 04:00:07 +0100, > Anshuman Khandual <anshuman.khandual@arm.com> wrote: > > > > Currently PMSNEVFR_EL1 system register read, and write access EL2 traps are > > disabled, via setting the same bit (i.e 62) in HDFGRTR_EL2, and HDFGWTR_EL2 > > respectively. Although very similar, bit fields are not exact same in these > > two EL2 trap configure registers particularly when it comes to read-only or > > write-only accesses such as ready-only 'HDFGRTR_EL2.nBRBIDR' which needs to > > be set while enabling BRBE on NVHE platforms. Using the exact same bit mask > > fields for both these trap register risk writing into their RESERVED areas, > > which is undesirable. > > Sorry, I don't understand at all what you are describing. You seem to > imply that the read and write effects of the FGT doesn't apply the > same way. But my reading of the ARM ARM is that behave completely > symmetrically.
nBRBIDR is an asymmetric bit (bit 59 of HDFGWTR_EL2 is RES0). While the architecture *could* repurpose this WTR bit for something else, that feels rather implementation and software hostile. I don't think there's a practical issue here, especially since the architecture has already allocated another pair of debug trap registers to make room for more bits.
> So what has changed here, aside from clobbering an extra register? The > masks are the same, the initial values are the same... Is it in > preparation for some other work?
Yeah, it feels as though this patch is taken out of context. Without a justifying functional change I don't see the value in fiddling with this code.
-- Thanks, Oliver
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