lkml.org 
[lkml]   [2023]   [Oct]   [18]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
    Patch in this message
    /
    From
    Subject[PATCH v12 05/20] cxl/port: Pre-initialize component register mappings
    Date
    The component registers of a component may not exist and
    cxl_setup_comp_regs() will fail for that reason. In another case,
    Software may not use and set those registers up. cxl_setup_comp_regs()
    is then called with a base address of CXL_RESOURCE_NONE. Both are
    valid cases, but the function returns without initializing the
    register map.

    Now, a missing component register block is not necessarily a reason to
    fail (feature is optional or its existence checked later). Change
    cxl_setup_comp_regs() to also use components with the component
    register block missing. Thus, always initialize struct
    cxl_register_map with valid values, set @dev and make @resource
    CXL_RESOURCE_NONE.

    The change is in preparation of follow-on patches.

    Signed-off-by: Terry Bowman <terry.bowman@amd.com>
    Signed-off-by: Robert Richter <rrichter@amd.com>
    Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
    ---
    drivers/cxl/core/port.c | 12 +++++++-----
    1 file changed, 7 insertions(+), 5 deletions(-)

    diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
    index b993dea61436..28ba8922d0a4 100644
    --- a/drivers/cxl/core/port.c
    +++ b/drivers/cxl/core/port.c
    @@ -694,16 +694,18 @@ static struct cxl_port *cxl_port_alloc(struct device *uport_dev,
    static int cxl_setup_comp_regs(struct device *host, struct cxl_register_map *map,
    resource_size_t component_reg_phys)
    {
    - if (component_reg_phys == CXL_RESOURCE_NONE)
    - return 0;
    -
    *map = (struct cxl_register_map) {
    .host = host,
    - .reg_type = CXL_REGLOC_RBI_COMPONENT,
    + .reg_type = CXL_REGLOC_RBI_EMPTY,
    .resource = component_reg_phys,
    - .max_size = CXL_COMPONENT_REG_BLOCK_SIZE,
    };

    + if (component_reg_phys == CXL_RESOURCE_NONE)
    + return 0;
    +
    + map->reg_type = CXL_REGLOC_RBI_COMPONENT;
    + map->max_size = CXL_COMPONENT_REG_BLOCK_SIZE;
    +
    return cxl_setup_regs(map);
    }

    --
    2.30.2
    \
     
     \ /
      Last update: 2023-10-18 19:31    [W:2.580 / U:0.032 seconds]
    ©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site