Messages in this thread | | | Date | Fri, 13 Oct 2023 16:23:15 +0100 | Subject | Re: [PATCH 1/2] dt-bindings: w1: Add YAML DT Schema for AMD w1 master and MAINTAINERS entry | From | Kris Chaplin <> |
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On 13/10/2023 16:07, Conor Dooley wrote: > On Fri, Oct 13, 2023 at 05:04:32PM +0200, Krzysztof Kozlowski wrote: >> >> That's a quite generic compatible. axi is ARM term, 1-wire is the name >> of the bus and master is the role. Concatenating three common words does >> not create unique device name. Compatibles are supposed to be specific >> and this is really relaxed. Anything can be over AXI, everything in >> 1wire is 1wire and every master device is a master. > Given the vendor (and the title of the binding) this is almost certainly > an FPGA IP core, so the generic name is understandable. Using the exact > name of the IP in the AMD/Xilinx catalog probably is the best choice?
Indeed this is an Programmable Logic IP core - the official name of the core in our catalog is axi_1wire_master. It is a soft HDL core.
regards,
Kris
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