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    Subject[tip: perf/core] x86/cpu: Fix the AMD Fam 17h, Fam 19h, Zen2 and Zen4 MSR enumerations
    The following commit has been merged into the perf/core branch of tip:

    Commit-ID: deedec0a152a3d7fa5b04ef9431aeb71802835b5
    Gitweb: https://git.kernel.org/tip/deedec0a152a3d7fa5b04ef9431aeb71802835b5
    Author: Borislav Petkov <bp@alien8.de>
    AuthorDate: Thu, 12 Oct 2023 20:01:59 +02:00
    Committer: Ingo Molnar <mingo@kernel.org>
    CommitterDate: Thu, 12 Oct 2023 20:10:39 +02:00

    x86/cpu: Fix the AMD Fam 17h, Fam 19h, Zen2 and Zen4 MSR enumerations

    The comments introduced in <asm/msr-index.h> in the merge conflict fixup in:

    8f4156d58713 ("Merge branch 'x86/urgent' into perf/core, to resolve conflict")

    ... aren't right: AMD naming schemes are more complex than implied,
    family 0x17 is Zen1 and 2, family 0x19 is spread around Zen 3 and 4.

    So there's indeed four separate MSR namespaces for:

    MSR_F17H_
    MSR_F19H_
    MSR_ZEN2_
    MSR_ZEN4_

    ... and the namespaces cannot be merged.

    Fix it up. No change in functionality.

    Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
    Signed-off-by: Ingo Molnar <mingo@kernel.org>
    Cc: Peter Zijlstra <peterz@infradead.org>
    Link: https://lore.kernel.org/r/D99589F4-BC5D-430B-87B2-72C20370CF57@exactcode.com
    ---
    arch/x86/include/asm/msr-index.h | 20 +++++++++++---------
    1 file changed, 11 insertions(+), 9 deletions(-)

    diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
    index 0ad9ba8..f8b5028 100644
    --- a/arch/x86/include/asm/msr-index.h
    +++ b/arch/x86/include/asm/msr-index.h
    @@ -637,18 +637,20 @@
    /* AMD Last Branch Record MSRs */
    #define MSR_AMD64_LBR_SELECT 0xc000010e

    -/* Fam 19h (Zen 4) MSRs */
    -#define MSR_F19H_UMC_PERF_CTL 0xc0010800
    -#define MSR_F19H_UMC_PERF_CTR 0xc0010801
    -
    -#define MSR_ZEN4_BP_CFG 0xc001102e
    +/* Zen4 */
    +#define MSR_ZEN4_BP_CFG 0xc001102e
    #define MSR_ZEN4_BP_CFG_SHARED_BTB_FIX_BIT 5

    -/* Fam 17h (Zen 2) MSRs */
    -#define MSR_F17H_IRPERF 0xc00000e9
    +/* Fam 19h MSRs */
    +#define MSR_F19H_UMC_PERF_CTL 0xc0010800
    +#define MSR_F19H_UMC_PERF_CTR 0xc0010801

    -#define MSR_ZEN2_SPECTRAL_CHICKEN 0xc00110e3
    -#define MSR_ZEN2_SPECTRAL_CHICKEN_BIT BIT_ULL(1)
    +/* Zen 2 */
    +#define MSR_ZEN2_SPECTRAL_CHICKEN 0xc00110e3
    +#define MSR_ZEN2_SPECTRAL_CHICKEN_BIT BIT_ULL(1)
    +
    +/* Fam 17h MSRs */
    +#define MSR_F17H_IRPERF 0xc00000e9

    /* Fam 16h MSRs */
    #define MSR_F16H_L2I_PERF_CTL 0xc0010230
    \
     
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