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SubjectRe: [PATCH v1 5/5] arm64: dts: qcom: sa8775p: Add ep pcie0 controller node
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On 9/21/2023 3:18 PM, Manivannan Sadhasivam wrote:
> On Wed, Sep 20, 2023 at 07:25:12PM +0530, Mrinmay Sarkar wrote:
>> Add ep pcie dtsi node for pcie0 controller found on sa8775p platform.
>>
> It would be good to add more info in the commit message, like PCIe Gen, lane
> info, IP revision etc...
>
>> Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com>
>> ---
>> arch/arm64/boot/dts/qcom/sa8775p.dtsi | 45 +++++++++++++++++++++++++++++++++++
>> 1 file changed, 45 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
>> index 9f4f58e8..5571131 100644
>> --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
>> @@ -2600,4 +2600,49 @@
>>
>> status = "disabled";
>> };
>> +
>> + pcie0_ep: pcie-ep@1c00000 {
>> + compatible = "qcom,sa8775p-pcie-ep";
>> + reg = <0x0 0x01c00000 0x0 0x3000>,
>> + <0x0 0x40000000 0x0 0xf20>,
>> + <0x0 0x40000f20 0x0 0xa8>,
>> + <0x0 0x40001000 0x0 0x4000>,
>> + <0x0 0x40200000 0x0 0x100000>,
>> + <0x0 0x01c03000 0x0 0x1000>,
>> + <0x0 0x40005000 0x0 0x2000>;
>> + reg-names = "parf", "dbi", "elbi", "atu", "addr_space",
>> + "mmio", "dma";
>> +
>> + clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
>> + <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
>> + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
>> + <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
>> + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>;
>> +
>> + clock-names = "aux",
>> + "cfg",
>> + "bus_master",
>> + "bus_slave",
>> + "slave_q2a";
>> +
>> + interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 630 IRQ_TYPE_LEVEL_HIGH>;
>> +
>> + interrupt-names = "global", "doorbell", "dma";
>> +
>> + interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>,
>> + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>;
>> + interconnect-names = "pcie-mem", "cpu-pcie";
>> +
> Don't you need iommu property?
>
>> + resets = <&gcc GCC_PCIE_0_BCR>;
>> + reset-names = "core";
>> + power-domains = <&gcc PCIE_0_GDSC>;
>> + phys = <&pcie0_phy>;
>> + phy-names = "pciephy";
>> + max-link-speed = <3>;
> Gen 3?
there is some stability issue with gen4 so going with gen3 as of now.
Will update once issue is resolved.

Thanks,
Mrinmay
>> + num-lanes = <2>;
> Only 2 lanes? Or the other one has 4 lanes?
>
> - Mani
pcie0 has lane2 and pcie1 has lane4 configuration.

Thanks,
Mrinmay
>> +
>> + status = "disabled";
>> + };
>> };
>> --
>> 2.7.4
>>

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