Messages in this thread | | | From | "Manne, Nava kishore" <> | Subject | RE: [PATCH] fpga: versal: Add support for 44-bit DMA operations | Date | Tue, 10 Oct 2023 05:37:43 +0000 |
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Hi Yilun,
Thanks for providing the review comments. Please find my response inline.
> -----Original Message----- > From: Xu Yilun <yilun.xu@linux.intel.com> > Sent: Saturday, October 7, 2023 12:47 PM > To: Manne, Nava kishore <nava.kishore.manne@amd.com> > Cc: mdf@kernel.org; hao.wu@intel.com; yilun.xu@intel.com; > trix@redhat.com; linux-fpga@vger.kernel.org; linux-kernel@vger.kernel.org; > Pandey, Radhey Shyam <radhey.shyam.pandey@amd.com> > Subject: Re: [PATCH] fpga: versal: Add support for 44-bit DMA operations > > On Tue, Oct 03, 2023 at 12:44:09PM +0530, Nava kishore Manne wrote: > > The existing implementation support only 32-bit DMA operation. > > So, it fails to load the bitstream for the high DDR designs(Beyond 4GB). > > To fix this issue update the DMA mask handling logic to support 44-bit > > This is the HW defined DMA addressing capability. Does the device only > support up to 44 bits DMA? Any Doc? > The versal platform supports a maximum physical address size is 44-bit in AArch64. For more details, please refer the Versal TRM (Memory space- section): https://docs.xilinx.com/r/en-US/am011-versal-acap-trm/Memory-Space
Regards, Navakishore.
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