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SubjectRe: [PATCH RFC 0/5] drm/msm: dpu1: correctly implement SSPP & WB Clock Control Split
On 10/10/2023 10:10, Marijn Suijten wrote:
> On 2023-10-09 18:36:11, Neil Armstrong wrote:
>> Starting with the SM8550 platform, the SSPP & WB Clock Controls are
>> no more in the MDP TOP registers, but in the SSPP & WB register space.
>>
>> Add the corresponding SSPP & WB ops and use them from the vbif QoS
>> and OT limit setup functions.
>>
>> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
>> ---
>> Neil Armstrong (5):
>> drm/msm: dpu1: create a dpu_hw_clk_force_ctrl() helper
>> drm/msm: dpu1: add setup_clk_force_ctrl() op to sspp & wb
>> drm/msm: dpu1: vbif: add dpu_vbif_setup_clk_force_ctrl() helper
>> drm/msm: dpu1: call wb & sspp clk_force_ctrl op if split clock control
>> drm/msm: dpu1: sm8550: move split clock controls to sspp entries
>
> Fyi we're all using drm/msm/dpu: now :)

Ack, thx, will change for v2

>
> - Marijn
>
>>
>> .../gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 35 +++++++++-----------
>> .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 4 +--
>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 4 +++
>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 9 +++++
>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 9 +++++
>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c | 23 +------------
>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c | 21 ++++++++++++
>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h | 4 +++
>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c | 9 +++++
>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h | 4 +++
>> drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 9 +++--
>> drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c | 38 +++++++++++++++++-----
>> drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.h | 12 ++++---
>> 13 files changed, 120 insertions(+), 61 deletions(-)
>> ---
>> base-commit: 9119cf579b4432b36be9d33a92f4331922067d92
>> change-id: 20231009-topic-sm8550-graphics-sspp-split-clk-43c32e37b6aa
>>
>> Best regards,
>> --
>> Neil Armstrong <neil.armstrong@linaro.org>
>>

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