Messages in this thread | | | Date | Tue, 10 Oct 2023 15:21:16 +0800 | Subject | Re: [PATCH v2 6/7] riscv: dts: sophgo: add initial CV1812H SoC device tree | From | Chen Wang <> |
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On 2023/10/9 19:26, Inochi Amaoto wrote: > Add initial device tree for the CV1812H RISC-V SoC by SOPHGO. > > Signed-off-by: Inochi Amaoto <inochiama@outlook.com> > --- > arch/riscv/boot/dts/sophgo/cv1812h.dtsi | 36 +++++++++++++++++++++++++ > 1 file changed, 36 insertions(+) > create mode 100644 arch/riscv/boot/dts/sophgo/cv1812h.dtsi > > diff --git a/arch/riscv/boot/dts/sophgo/cv1812h.dtsi b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi > new file mode 100644 > index 000000000000..3864d34b0100 > --- /dev/null > +++ b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi > @@ -0,0 +1,36 @@ > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > +/* > + * Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com> > + */ > + > +#include <dt-bindings/interrupt-controller/irq.h> This include is not required. > +#include "cv180x.dtsi" > + > +/ { > + compatible = "sophgo,cv1812h"; > + > + memory@80000000 { > + device_type = "memory"; > + reg = <0x80000000 0x10000000>; > + }; What's this defined for , I see this is different against cv1800b. > + > + soc { > + interrupt-parent = <&plic>; > + > + plic: interrupt-controller@70000000 { > + compatible = "sophgo,cv1812h-plic", "thead,c900-plic"; > + reg = <0x70000000 0x4000000>; > + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>; > + interrupt-controller; > + #address-cells = <0>; > + #interrupt-cells = <2>; > + riscv,ndev = <101>; > + }; > + > + clint: timer@74000000 { > + compatible = "sophgo,cv1812h-clint", "thead,c900-clint"; > + reg = <0x74000000 0x10000>; > + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>; > + }; > + }; > +}; > -- > 2.42.0 >
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