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SubjectRe: [RESEND RFC PATCH v5 3/5] ARM: dts: stm32: add CAN support on stm32f429
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On 1/8/23 17:25, Dario Binacchi wrote:
> Add support for bxcan (Basic eXtended CAN controller) to STM32F429. The
> chip contains two CAN peripherals, CAN1 the master and CAN2 the slave,
> that share some of the required logic like clock and filters. This means
> that the slave CAN can't be used without the master CAN.
>
> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
>
> ---
>
> (no changes since v4)
>
> Changes in v4:
> - Replace the node can@40006400 (compatible "st,stm32f4-bxcan-core")
> with the gcan@40006600 node ("sysnode" compatible). The gcan node
> contains clocks and memory addresses shared by the two can nodes
> of which it's no longer the parent.
> - Add to can nodes the "st,gcan" property (global can memory) which
> references the gcan@40006600 node ("sysnode compatibble).
>
> Changes in v3:
> - Remove 'Dario Binacchi <dariobin@libero.it>' SOB.
> - Add "clocks" to can@0 node.
>
> arch/arm/boot/dts/stm32f429.dtsi | 29 +++++++++++++++++++++++++++++
> 1 file changed, 29 insertions(+)
>
> diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
> index c31ceb821231..ce08872109b8 100644
> --- a/arch/arm/boot/dts/stm32f429.dtsi
> +++ b/arch/arm/boot/dts/stm32f429.dtsi
> @@ -362,6 +362,35 @@ i2c3: i2c@40005c00 {
> status = "disabled";
> };
>
> + gcan: gcan@40006600 {
> + compatible = "st,stm32f4-gcan", "syscon";
> + reg = <0x40006600 0x200>;
> + clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>;
> + };
> +
> + can1: can@40006400 {
> + compatible = "st,stm32f4-bxcan";
> + reg = <0x40006400 0x200>;
> + interrupts = <19>, <20>, <21>, <22>;
> + interrupt-names = "tx", "rx0", "rx1", "sce";
> + resets = <&rcc STM32F4_APB1_RESET(CAN1)>;
> + clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>;
> + st,can-master;
> + st,gcan = <&gcan>;
> + status = "disabled";
> + };

We try to keep ordering by address. Can you move can1 before gcan ?
Otherwise, it is ok for me.

> +
> + can2: can@40006800 {
> + compatible = "st,stm32f4-bxcan";
> + reg = <0x40006800 0x200>;
> + interrupts = <63>, <64>, <65>, <66>;
> + interrupt-names = "tx", "rx0", "rx1", "sce";
> + resets = <&rcc STM32F4_APB1_RESET(CAN2)>;
> + clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN2)>;
> + st,gcan = <&gcan>;
> + status = "disabled";
> + };
> +
> dac: dac@40007400 {
> compatible = "st,stm32f4-dac-core";
> reg = <0x40007400 0x400>;

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