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Subject[PATCH 4/8] Documentation: kvx: kvx-iommu: Use reST syntax for subsections
Subsection headings of "IOMMU implementation" is written using
triple-hash syntax, which is valid only for Markdown. Since the
documentation is written in reST, use appropriate syntax instead
(tilde underline).

Signed-off-by: Bagas Sanjaya <>
Documentation/kvx/kvx-iommu.rst | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/Documentation/kvx/kvx-iommu.rst b/Documentation/kvx/kvx-iommu.rst
index f7f61777eee21e..5ed34463b8bb1f 100644
--- a/Documentation/kvx/kvx-iommu.rst
+++ b/Documentation/kvx/kvx-iommu.rst
@@ -110,7 +110,8 @@ the cluster.
IOMMU is related to a specific bus like PCIe we will be able to specify that
all peripherals will go through this IOMMU.

-### IOMMU Page table
+IOMMU Page table

We need to be able to know which IO virtual addresses (IOVA) are mapped in the
TLB in order to be able to remove entries when a device finishes a transfer and
@@ -137,7 +138,8 @@ huge page table for a given IOMMU (typically the PCIe IOMMU).
As we won't refill the TLB we know that we won't have more than 128*16 entries.
In this case we can simply keep a table with all possible entries.

-### Maintenance interface
+Maintenance interface

It is possible to have several "maintainers" for the same IOMMU. The driver is
using two of them. One that writes the TLB and another interface reads TLB. For
@@ -149,7 +151,8 @@ following command in gdb:
Since different management interface are used for read and write it is safe to
execute the above command at any moment.

-### Interrupts

IOMMU can have 3 kind of interrupts that corresponds to 3 different types of
errors (no mapping. protection, parity). When the IOMMU is shared between
@@ -163,7 +166,8 @@ stall one. So when an interrupt occurs it is managed by the driver. All others
interrupts that occurs are stored and the IOMMU is stalled. When driver cleans
the first interrupt others will be managed one by one.

-### ASN (Address Space Number)
+ASN (Address Space Number)

This is also know as ASID in some other architecture. Each device will have a
given ASN that will be given through the device tree. As address space is
An old man doll... just what I always wanted! - Clara
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